Fusion Compiler App Options

Complete Synopsys Fusion Compiler application options — Physical Synthesis, Clock Gating, CTS, Routing, Chip Finishing, IC Validator, RedHawk Fusion, ECO Flow, Hierarchical Implementation and more.

13 chapters · All content free to read

1. Ch 1Power Intent, Determinism and DRC Flow4 options
2. Ch 2Library Optimization and CTS Topology117 options
3. Ch 3Logic Restructuring and Hierarchical Cells78 options
4. Ch 4Clock Gating Controls and Level Expansion26 options
5. Ch 5Clock Power Recovery and Design Modes119 options
6. Ch 6Via Protection and Congestion Management117 options
7. Ch 7Diode Insertion and Antenna Repair36 options
8. Ch 8Power Grid Augmentation and Workspace76 options
9. Ch 9Custom Routing and Balance Configuration37 options
10. Ch 10Placement Constraint Tuning1 options
11. Ch 11Abstract Annotation and Path Group Timing68 options
12. Ch 12Liberty Validation and Power Integrity48 options
13. Ch 13ECO Flow and Freeze Silicon Control12 options