| 1 | opt.common.enable_target_librar y_subset_opt | Enables the use of the target library subset during optimization. The subset restriction applies to hierarchical cells but not to leaf cells, and is enforced on the specified blocks and their subdesigns in the hierarchy (except subdesigns where a different subset restriction is set). A subset specified at a lower level supersedes any subset specified at a higher level | set_app_options -name opt.common.enable_target_library_subset_opt -value 1 |
| 2 | cts.compile.topological_ndr | Enables the level-based clock nondefault routing rule application, ensuring all nondefault routing rules in a clock tree path are in topologically sorted order from clock root to sinks (Root NDR > Internal NDR > Sink NDR) | fc_shell> set_app_options -list {cts.compile.topological_ndr true} |
| 3 | opt.common.enable_target_librar y_subset_opt | Enables target library subset optimization so that library restrictions defined with set_target_library_subset (such as using only cells from a specific library for a block and its subblocks) are honored during optimization and clock tree synthesis | fc_shell> set_app_options -name opt.common.enable_target_library_subset_opt -value 1 |
| 4 | route.common.net_max_layer_m ode_soft_cost | Sets the cost of violating soft constraints for all net-specific maximum layer constraints. Controls the effort the router expends to avoid violations | |
| 5 | pin_check.place.preplace_option _file | Sets the preplacement option file used by the pin access checker utility (check_libcell_pin_access). Set as a user default for pin access checking | set_app_options -as_user_default -name pin_check.place.preplace_option_file -value |
| 6 | route.common.net_min_layer_m ode_soft_cost | Sets the cost of violating soft constraints for all net-specific minimum layer constraints. Controls the effort the router expends to avoid violations | |
| 7 | libra.complib.match_full_cell_na me | Controls whether the compare_libraries command matches cells by their full cell name. Set to false when the reference and target library naming conventions differ partially (requiring a lexical attribute mapping file via -lex_attr_mapping) or completely (requiring a custom cell-pair mapping file via -custom_pairs) | fc_shell> set_app_options -name libra.complib.match_full_cell_name -value true |
| 8 | route.common.net_max_layer_m ode | Changes the default constraint strength for all net-specific maximum layer constraints. By default, net-specific maximum layer constraints are hard constraints | |
| 9 | mv.pg.create_floating_pg | Enables the creation of floating logical supply nets (power or ground nets not connected to any logical pin or port in the block). Must be set to true before you create supply nets with the connect_pg_net command | set_app_options -as_user_default -name mv.pg.create_floating_pg -value true |
| 10 | route.common.net_min_layer_m ode | Changes the default constraint strength for all net-specific minimum layer constraints. By default, net-specific minimum layer constraints are soft constraints | |
| 11 | place.coarse.ir_drop_default_tar get_low_population | Controls the default target for the lower-population (middle) cell category used in IR-drop-aware placement. Shown set to false in the example | set_app_options -name place.coarse.ir_drop_default_target_low_population -value true |
| 12 | route.common.global_max_layer _mode | Changes the maximum routing layer constraint type from soft to hard | set_app_options -name route.common.global_max_layer_mode -value hard |
| 13 | place.coarse.ir_drop_default_tar get_low_percentage | Sets the default percentage of cells assigned to the lower/middle target category for IR-drop-aware placement. Shown set to 4.0 in the example | set_app_options -name place.coarse.ir_drop_default_target_low_percentage -value 4.0 |
| 14 | route.common.global_min_layer_ mode | Changes the minimum routing layer constraint type from soft to hard | set_app_options -name route.common.global_min_layer_mode -value hard |
| 15 | place.coarse.spread_repeater_p aths | Reduces congestion caused by chains of repeater cells (buffers, inverters, or pipelined registers) clumped along the edges or corners of macro cells or blockages. When set to true, the tool spreads the repeater cells in an orthogonal direction to reduce congestion along edges and corners | set_app_options -name place.coarse.spread_repeater_paths -value true |
| 16 | clock_opt.flow.enable_irap | Manually enables voltage-drop-aware placement for the clock_opt command | fc_shell> set_app_option -name clock_opt.flow.enable_irap -value true |
| 17 | place.legalize.optimize_orientatio ns | Enables orientation optimization during legalization. When set to true, the tool considers flipping the orientations of cells to reduce the displacements during legalization | |
| 18 | compile.flow.enable_irap | Manually enables voltage-drop-aware placement for the compile_fusion command | fc_shell> set_app_option -name compile.flow.enable_irap -value true |
| 19 | place.legalize.stream_place | Enables stream placement during legalization. When set to true, the tool moves many cells a small distance, to avoid moving a single cell a large distance during legalization | |
| 20 | compile.flow.enable_dps | Manually enables dynamic power shaping for the compile_fusion command | fc_shell> set_app_option -name compile.flow.enable_dps -value true |
| 21 | place.legalize.stream_effort | Controls the effort of stream placement during legalization | |
| 22 | opt.common.power_integrity | Controls power integrity mode for the compile_fusion and clock_opt commands. Must be set to false to manually enable dynamic power shaping or voltage-drop-aware placement | fc_shell> set_app_option -name opt.common.power_integrity -value true |
| 23 | place.legalize.stream_effort_limit | Controls the effort limit of stream placement during legalization | |
| 24 | rail.analysis_type | Sets the voltage-drop-analysis type for voltage-drop-aware placement setup | |
| 25 | place.legalize.optimize_pin_acce ss_using_cell_spacing | For advanced technology nodes, enables pin optimization during legalization to improve the routability of areas with high pin densities by redistributing the cells | |
| 26 | ccd.dps.auto_target_constraint_p arameters | Controls automatic target constraint parameters for dynamic power shaping during CCD flow | |
| 27 | place.legalize.enable_advanced_ prerouted_net_check | For advanced technology nodes, such as 12 nanometer, 7 nanometer, or smaller technology nodes, enables advanced physical DRC checks between cells and prerouted PG nets | |
| 28 | ccd.dps.auto_targets | Controls automatic targets for dynamic power shaping during CCD flow | |
| 29 | place.legalize.advanced_layer_a ccess_check | Controls the accessibility checks performed for standard cell pins when advanced prerouted net checks are enabled | |
| 30 | ccd.dps.use_cases | Controls use cases for dynamic power shaping during CCD flow. More complex option for controlling power analysis and optimization during dynamic power shaping | |
| 31 | place.legalize.advanced_libpin_a ccess_check | Controls the accessibility checks performed for standard cell pins when advanced prerouted net checks are enabled | |
| 32 | clock_opt.flow.enable_irdrivenopt | Enables IR-driven sizing, which uses RedHawk dynamic voltage drop results to replace high-voltage-drop cells with lower-leakage alternatives | fc_shell> set_app_options -name clock_opt.flow.enable_irdrivenopt -value true |
| 33 | place.legalize.enable_threaded_ advanced_legalizer | Enables multithreaded advanced legalization algorithms | |
| 34 | opt.common.ir_drop_threshold | Sets the maximum voltage drop threshold as a percentage of supply voltage for power integrity optimization | fc_shell> set_app_options -name opt.common.ir_drop_threshold -value 10 |
| 35 | place.legalize.enable_advanced_ legalizer | Enables advanced legalization algorithms, used to perform multithreaded advanced legality checking | |
| 36 | opt.common.power_integrity_effo rt | Controls the effort level for power integrity optimization; determines whether the tool will reduce voltage drop at the expense of timing QoR | fc_shell> set_app_options -name opt.common.power_integrity_effort -value minimal |
| 37 | place.legalize.enable_variant_aw are | Enables variant-aware legalization. When enabled, the tool tries to fix legalization DRC violations by swapping the violating cell with a variant, rather than moving it. If the cell has no variants, it is moved to a legal location | |
| 38 | opt.common.power_integrity | Enables the recommended power integrity flow, activating dynamic power shaping (DPS) during compile_fusion and voltage-drop-aware placement during clock_opt | fc_shell> set_app_options -name opt.common.power_integrity -value true |
| 39 | place.legalize.enable_prerouted_ net_check | For pin-track and pin-color alignment during variant-aware legalization, set this application option to true | |
| 40 | power.scale_leakage_power_at_ power_off | Controls whether leakage power is scaled based on the supply switching activity when a power domain is powered off | |
| 41 | place.legalize.enable_pin_color_ alignment_check | For pin-track and pin-color alignment during variant-aware legalization, set this application option to true | |
| 42 | power.scale_dynamic_power_at _power_off | Controls whether dynamic power is scaled based on the supply switching activity when a power domain is powered off | |
| 43 | place.legalize.pin_color_alignme nt_layers | Sets the layers to be aligned for pin-color alignment during variant-aware legalization | |
| 44 | power.use_generated_clock_sca ling_factor | Enables scaling of the switching activity associated with generated clock nets using a ratio specified by the set_power_clock_scaling command | fc_shell> set_app_options -list {power.use_generated_clock_scaling_factor true} |
| 45 | design.uniquify_naming_style | Controls the names of the reference copies created by the uniquify process. %s denotes the name of the existing reference and %d denotes the smallest integer value that forms a unique design name | |
| 46 | opt.common.advanced_logic_res tructuring_mode | Controls advanced logic restructuring to improve area, timing, and power QoR during the final_opto stage of compile_fusion and clock_opt commands | fc_shell> set_app_options -name opt.common.advanced_logic_restructuring_mode -value timing |
| 47 | opt.common.preserve_pin_name s | Restricts the sizing capability so that constraints remain unchanged through optimization. By default, optimization can change the pin names of leaf cells during sizing if the functionality of the resulting circuit is equivalent. Setting The option preserves pin names so that the original constraints used to constrain the block remain valid | |
| 48 | opt.common.small_region_area_ recovery | Specifies that the tool perform area recovery in regions where the utilization is high, for designs that cannot be legalized due to areas of high utilization | fc_shell> set_app_options -name opt.common.small_region_area_recovery -value true |
| 49 | opt.port.eliminate_verilog_assign | Enables multiple-port-net fixing for the initial_opto and final_opto stages (later stages of the compile_fusion command). Multiple-port nets are represented with the assign statement in the gate-level netlist and might cause design rule violations further in the design flow. If set to true without an explicit set_fix_multiple_port_nets setting, the tool internally runs set_fix_multiple_port_nets -all -buffer_constants to fix multiple-port nets during the logic_opto and initial_drc stages (message MPN-0004) | |
| 50 | compile.flow.optimize_ndr_max_ nets | Sets the maximum number of nets considered for automatic nondefault routing rules assignment. When both compile.flow.optimize_ndr_critical_range and The option are specified, the stricter constraint has priority | fc_shell> set_app_options -name compile.flow.optimize_ndr_max_nets -value 5000 |
| 51 | opt.common.user_instance_nam e_prefix | Specifies a name prefix for the cells added on the data nets during optimization (compile_fusion, clock_opt, and route_opt commands) | fc_shell> set_app_options -name opt.common.user_instance_name_prefix -value "CF_" |
| 52 | compile.flow.optimize_ndr_critica l_range | Sets the critical range for nondefault routing rule assignment. The value y is used to calculate the slack range [y*WNS, WNS] where WNS is the worst negative slack. Nets in timing paths with slack within this range are considered for NDR assignment | fc_shell> set_app_options -name compile.flow.optimize_ndr_critical_range -value y |
| 53 | cts.common.user_instance_nam e_prefix | Specifies a name prefix for the cells added on the clock network during clock tree synthesis | |
| 54 | compile.flow.optimize_ndr | Enables the automatic assignment of nondefault routing rules to timing-critical nets during optimization | set compile.flow.optimize_ndr |
| 55 | power.leakage_mode | Controls the leakage power calculation mode used by the report_power command. By default, state-dependent leakage power is used to calculate leakage power; set The option to change the calculation mode | set_app_options -name power.leakage_mode -value average |
| 56 | opt.common.optimize_ndr_user_ rule_names | Specifies a prioritized list of nondefault routing rules for automatic assignment to timing-critical nets during optimization. Rules are tried in order of priority | set opt.common.optimize_ndr_user_rule_names { ndr_1w2s ndr_2w3s } |
| 57 | ccd.dps.focus_power_scenario | Sets the scenarios to focus on during dynamic power shaping. By default, the tool focuses on all active scenarios. When the design has many active scenarios, specifying one or two scenarios can reduce the runtime | set_app_options -name -name ccd.dps.focus_power_scenario -value {{S1 S2}} |
| 58 | route.global.insert_gr_via_ladder s | Enables insertion of global-route-based via ladders on pins with via ladder constraints during preroute optimization | |
| 59 | ccd.dps.use_case_type | Controls the type of internal power analysis performed during dynamic power shaping. With autovector, the tool runs internal power analysis with a 20 percent probability of toggling a flip-flop and all flip-flops are effectively clocked every cycle, but clock gating is not modeled. With activity, the tool chooses probability of toggling a flip-flop and the clock-gating model based on the activity | |
| 60 | opt.common.enable_via_ladder_i nsertion | Enables high-performance and electromigration via ladder insertion for critical paths during compile_fusion and clock_opt commands. Via ladders are stacked vias starting from the pin layer extending into upper routing layers, reducing via resistance to improve performance and electromigration robustness | |
| 61 | ccd.dps.optimize_power_target_ modes | Establishes the overall dynamic power optimization goal. Set to global_peak to reduce the global peak current (optimization goal is to reduce the total peak current). Set to stepped_psgs to reduce the local peak current in windows stepped across the design (optimization goal is to reduce voltage drop violations) | |
| 62 | opt.common.use_route_aware_e stimation | Enables global-route-layer-based (GRLB) RC estimation. When route-driven estimation is enabled, this application option is ignored | |
| 63 | ccd.dps.optimize_setup_tradeoff _level | Sets the tradeoff between power and setup timing during dynamic power shaping | |
| 64 | opt.common.enable_rde | Enables Route-Driven Estimation (RDE) during the final_opt stage of compile_fusion and clock_opt. Tool performs global routing and extraction for better parasitic estimation | set_app_options -name opt.common.enable_rde -value true |
| 65 | ccd.dps.optimize_hold_tradeoff_l evel | Sets the tradeoff between power and hold timing during dynamic power shaping | |
| 66 | opt.common.use_route_aware_e stimation | Enables global-route-layer-based RC estimation during compile_fusion and clock_opt to improve preroute/postroute correlation. 'auto' enables only when layer resistance varies; 'true' always enables | set_app_options -name opt.common.use_route_aware_estimation -value true |
| 67 | route.common.global_min_layer_ mode | Controls the strength of the global minimum routing layer constraint. Set to allow_pin_connection to allow the use of layers beyond the minimum routing layer only for pin connections | set the route.common.global_min_layer_mode and route.common.global_max_layer_mode application options to allow_pin_connection |
| 68 | opt.port.eliminate_verilog_assign | Enables elimination of Verilog assign statements during multiple-port-net fixing. When enabled, the tool fixes feedthrough nets during the initial_opto and final_opto stages of the compile_fusion command | fc_shell> set_app_options -name opt.port.eliminate_verilog_assign -value true |
| 69 | route.common.global_max_layer _mode | Controls the strength of the global maximum routing layer constraint. Set to allow_pin_connection to allow the use of layers beyond the maximum routing layer only for pin connections | set the route.common.global_min_layer_mode and route.common.global_max_layer_mode application options to allow_pin_connection |
| 70 | opt.common.preserve_pin_name s | Controls whether pin names are preserved during optimization. When set to 'always', sizing is restricted to pin-name equivalent cells | fc_shell> set_app_options -name opt.common.preserve_pin_names -value always |
| 71 | pin_check.place.preplace_option _file | Sets the name of a Tcl script that defines routing direction for metal layers, required as input for the create_pin_check_lib command when using the Pin Access Checker utility | |
| 72 | place.legalize.preroute_shape_m erge_distance | Sets the distance within which prerouted shapes are merged during legalization accessibility analysis | |
| 73 | libra.complib.match_full_cell_na me | Controls whether the tool requires full cell name matching when comparing libraries; set to false to allow partial name matching when one library has fewer lexical attributes | fc_shell> set_app_options -name libra.complib.match_full_cell_name -value true |
| 74 | place.legalize.reduce_conservati sm_in_eol_check | Reduces conservatism in end-of-line spacing checks during legalization accessibility analysis | |
| 75 | libra.complib.match_lexical_devi ce_threshold_voltage | Controls whether the lexical_device_threshold_voltage attribute is used for cell name matching when comparing libraries; set to false to ignore this attribute during comparison | fc_shell> set_app_options -name libra.complib.matc h_lexical_device_threshold_voltage -value true |
| 76 | place.legalize.allow_touch_track _for_access_check | Allows cells to touch routing tracks during accessibility checks in legalization | |
| 77 | hdlin.hdl_library.default_dirname | Controls the directory location where HDL template libraries are created on disk by the analyze command | |
| 78 | place.legalize.use_eol_spacing_f or_access_check | Enables use of end-of-line spacing rules during accessibility checks in legalization | |
| 79 | hdlin.hdl_library.default_name | Sets the default library name used by the analyze command when the -hdl_library option is not specified | |
| 80 | place.legalize.num_tracks_for_a ccess_check | Sets the number of routing tracks used for accessibility checking during legalization | |
| 81 | hdlin.autoread.verilog_extension s | Controls the file name extensions recognized as Verilog files when using the analyze -autoread option | |
| 82 | place.legalize.enable_prerouted_ net_check | Enables checking for prerouted net accessibility during legalization placement analysis | |
| 83 | hdlin.autoread.sverilog_extensio ns | Controls the file name extensions recognized as SystemVerilog files when using the analyze -autoread option | |
| 84 | place.legalize.enable_multi_cell_ track_capacity_check | Analyzes the track capacity of the cell's pins and abutting neighbor cells to estimate routing track sufficiency | set_app_options -name place.legalize.enable_multi_ cell_track_capacity_check -value true |
| 85 | hdlin.autoread.vhdl_extensions | Controls the file name extensions recognized as VHDL files when using the analyze -autoread option | |
| 86 | place.legalize.enable_multi_cell_ access_check | Considers impact on a cell's pin access due to abutting neighbor cells and prerouted PG net shapes; enabled at last route_opt or after route_auto | set_app_options -name place.legalize.enable_multi_cell_access_check -value true |
| 87 | hdlin.autoread.exclude_extensio ns | Controls file name extensions to exclude from automatic reading when using the analyze -autoread option | |
| 88 | place.legalize.enable_multi_cell_ pnet_checks | Enables simultaneous DRC violation checking between multiple cells and PG net shapes during advanced legalization | set_app_options -name place.legalize.enable_multi_cell_pnet_checks -value true |
| 89 | hdlin.naming.template_naming_s tyle | Controls the naming style for parameterized modules when elaborating mixed netlist/RTL designs | |
| 90 | place.legalize.optimize_pin_acce ss_strategies | Specifies additional strategies for pin access optimization during advanced legalization | set_app_options -name place.legalize.optimize_pin_access_strategies -value horizontal_align |
| 91 | hdlin.naming.template_paramete r_style | Controls the parameter style used in names for parameterized modules | |
| 92 | place.legalize.enable_advanced_ legalizer_rules | Specifies additional advanced legalization rules not automatically detected | set_app_options -name place.legalize.enable_advanced_legalizer_rules -value |
| 93 | hdlin.naming.template_separator _style | Controls the separator style used in names for parameterized modules | |
| 94 | place.legalize.enable_advanced_ legalizer | Enables advanced legalization algorithms for 2D rule checking and cell interaction, which can reduce legalization runtime | set_app_options -name place.legalize.enable_advanced_legalizer -value true |
| 95 | compile.auto_floorplan.initialize | Controls whether the tool creates missing floorplan information during automatic floorplanning. 'auto' creates missing info but exits on inconsistency; 'true' always creates core and boundary; 'false' never creates and exits on missing/inconsistent info | # set_app_options -name compile.auto_floorplan.initialize -value manual |
| 96 | place.coarse.ir_drop_default_tar get_low_population | When true, uses percentage of total cell count to define the middle IR-drop category; when false, uses voltage drop as a percentage of supply voltage | fc_shell> set_app_options -name place.coarse.ir_drop_default_target_low_population -value true |
| 97 | compile.auto_floorplan.place_pin s | Controls whether the auto floorplan places existing pins. Determines if fixed, placed, or unplaced pins are repositioned during auto floorplanning | |
| 98 | place.coarse.ir_drop_default_tar get_high_population | When true, uses percentage of total cell count to define the upper IR-drop category; when false, uses voltage drop as a percentage of supply voltage | fc_shell> set_app_options -name place.coarse.ir_drop_default_target_high_population -value true |
| 99 | compile.auto_floorplan.place_ios | Controls whether the auto floorplan places existing IOs/pads. Determines if fixed, placed, or unplaced IOs are repositioned during auto floorplanning | |
| 100 | place.coarse.ir_drop_default_tar get_low_percentage | Percentage of total cells (by count) to place in the middle IR-drop category during coarse placement | fc_shell> set_app_options -name place.coarse.ir_drop_default_target_low_percentage -value 6.0 |
| 101 | compile.auto_floorplan.place_har d_macros | Controls whether the auto floorplan places existing hard macros. Determines if fixed, placed, or unplaced hard macros are repositioned during auto floorplanning | |
| 102 | place.coarse.ir_drop_default_tar get_high_percentage | Percentage of total cells (by count) to place in the upper IR-drop category during coarse placement | fc_shell> set_app_options -name place.coarse.ir_dro p_default_target_high_percentage -value 2.0 |
| 103 | compile.auto_floorplan.shape_vo ltage_areas | Controls whether the auto floorplan shapes existing voltage areas. Determines if fixed, placed, or unshaped voltage areas are reshaped during auto floorplanning | |
| 104 | opt.buffering.exclusive_hard_bou nd_buffering_mode | Controls whether newly added buffers during buffering can be placed inside exclusive hard move bounds. By default the tool can add new cells to an exclusive hard move bound if it improves QoR. Setting to 0 forces the tool to honor the exclusive hard move bound strictly | set_app_options -name opt.buffering.exclusive_hard_bound_buffering_mode -value 0 |
| 105 | compile.auto_floorplan.keep_bou nds | Controls whether existing bounds are preserved during auto floorplanning | |
| 106 | place.coarse.enable_enhanced_ soft_blockages | Prevents subsequent incremental placement from moving cells (added during legalization, optimization, and clock tree synthesis) out of soft blockage areas. When enabled, cells placed inside a soft blockage during CTS/opt/legalization remain there during incremental placement | set_app_options -name place.coarse.enable_enhanced_soft_blockages -value true |
| 107 | compile.auto_floorplan.keep_bou nds | Controls whether existing placement bounds are kept or removed during automatic floorplanning. 'auto' removes existing bounds if compile.auto_floorplan.place_hard_macros or compile.auto_floorplan.shape_voltage_areas is set to 'all' | |
| 108 | opt.common.max_fanout | Specifies a maximum fanout for data paths in a block. The tool tries to ensure that data path cells do not drive more than the specified maximum fanout during optimization. This is a soft optimization constraint; the maximum fanout design rule constraint (set_max_fanout) is not honored by the Fusion Compiler tool | |
| 109 | compile.auto_floorplan.keep_pla cement_blockages | Controls whether existing placement blockages are kept or removed during automatic floorplanning. 'auto' removes blockages if compile.auto_floorplan.place_hard_macros or compile.auto_floorplan.shape_voltage_areas is set to 'all' | |
| 110 | opt.buffering.enable_hierarchy_ mapping | Enables improved buffering techniques for fixing logical DRC violations on multivoltage nets during preroute optimization. Reduces number of buffers used but may slightly increase TNS or hold violations | set_app_options -name opt.buffering.enable_hierarchy_mapping -value true |
| 111 | compile.auto_floorplan.initialize | Controls whether the tool creates missing floorplan information during automatic floorplanning | # set_app_options -name compile.auto_floorplan.initialize -value manual |
| 112 | place.coarse.enable_advanced_ mv_cell_placement | Enables advanced multivoltage cell placement to reduce the length of multivoltage nets by placing cells closer to voltage area boundaries. Uses dual-rail buffers for optimization | set_app_options -name place.coarse.enable_advanced_mv_cell_placement -value true |
| 113 | compile.auto_floorplan.place_pin s | Controls pin placement behavior during automatic floorplanning | # set_app_options -name compile.auto_floorplan.place_pins -value unplaced |
| 114 | opt.common.allow_physical_feed through | Controls feedthrough buffering for voltage areas that do not have a specific voltage area rule and no default rule is defined. When set, determines whether physical feedthrough nets are allowed in voltage areas | |
| 115 | compile.auto_floorplan.place_ios | Controls I/O placement behavior during automatic floorplanning | # set_app_options -name compile.auto_floorplan.place_ios -value unplaced |
| 116 | compile.auto_floorplan.shape_vo ltage_areas | Controls voltage area shaping behavior during automatic floorplanning | # set_app_options -name compile.auto_floorplan.shape_voltage_areas -value unshaped |
| 117 | compile.auto_floorplan.place_har d_macros | Controls hard macro placement behavior during automatic floorplanning | # set_app_options -name compile.auto_floorplan.place_hard_macros -value unplaced |
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