Comprehensive study guides for semiconductor physical design — from first principles to full tapeout. Every topic covered with clear explanations, worked examples, diagrams and interview Q&A.
MOS transistors, CMOS gates, delay, power, memory (SRAM/DRAM), datapath and design-for-test.
Clock tree synthesis with simultaneous clock-and-data optimization for tighter timing closure.
Complete CTS reference — concepts, prerequisites, step-by-step workflow, verification and troubleshooting.
Timing constraints — clocks, generated clocks, I/O delays, path exceptions, OCV and MCMM.
ECO types, unconstrained and metal-only flows, signoff-driven ECO, spare cells and timing fixes.
UPF/CPF power intent, isolation cells, level shifters, retention flops and power-gating flows.
Simultaneous macro and standard-cell placement with MSV awareness and incremental tuning.
Power domains, supply networks, power gating, state retention, always-on logic and low-power sign-off.
Global routing, track assignment, detail routing, DRC convergence, SI and postroute optimization.
STA — cell delay, interconnect, setup/hold checks, MCMM, OCV, crosstalk, IR drop and sign-off.
Pre-CTS, post-CTS, post-route optimization, useful skew, SI fixes, leakage reduction and ECO closure.
Complete Innovus & Fusion Compiler application options — Setup, Flows, Design Planning, Implementation, CTS, Routing, IC Validator, RedHawk, ECO and more.
Synopsys Fusion Compiler application options — Physical Synthesis, Clock Gating, CTS, Routing, Chip Finishing, IC Validator, Hierarchical, RedHawk and ECO Flow.