| 1 | compile.clockgate.clock_gate_na me_prefix | Sets the prefix used in the naming convention for clock gates inserted by the tool. The clock-gate name follows the form prefix_base-name[_index] | set_app_options -name compile.clockgate.clock_gate_name_prefix -value clock_gate |
| 2 | compile.clockgate.substring_list_ for_dft_wrapper_dont_rename_ic gs | Restricts the renaming of pre-existing clock gates that drive wrapper cells only. Clock gates whose names match any substring in this list are not renamed during the DFT wrapper clock gate naming flow | set_app_options -name compile.clockgate.substring _list_for_dft_wrapper_dont_rename_icgs -value {clk_gate_ctl clk_gate_snps} |
| 3 | compile.clockgate.enable_level_ expansion | Allows the tool to expand the number of clock-gate levels by analyzing all clock gates and inserting additional clock gates to take advantage of shared enable signals. Must be set together with a nonzero compile.clockgate.max_number_of_levels | set_app_options -name compile.clockgate.enable_level_expansion -value true |
| 4 | compile.clockgate.self_gating | Enables self-gating optimization during compile_fusion; inserts self-gating logic to reduce dynamic power based on SAIF switching activity | set_app_options -name compile.clockgate.self_gating -value true |
| 5 | compile.clockgate.max_number_ of_levels | Sets the maximum number of allowed clock-gate levels. A value of 0 allows an infinite number of levels; however, to use the clock-gate level expansion capability, you must set The option to a nonzero value (in addition to setting compile.clockgate.enable_level_expansion to true) | set_app_options -name compile.clockgate.max_number_of_levels -value 4 |
| 6 | compile.clockgate.max_number_ of_levels | Sets the maximum number of clock-gate levels allowed. A value of 0 allows an infinite number of levels; values less than existing levels cause collapsing | fc_shell> set_app_options -name compile.clockgate.max_number_of_levels -value 2 |
| 7 | compile.clockgate.enable_activit y_driven_level_expansion | Controls activity-driven analysis during clock-gate level expansion. When clock-gate level expansion is enabled, the tool performs activity-driven analysis by default. If a SAIF file is not available, disable this feature by setting it to false. If clock-gate level expansion is disabled, the tool ignores The option | set_app_options -name compile.clockgate.enable_a ctivity_driven_level_expansion -value true |
| 8 | cts.compile.enable_cell_relocatio n | Enables automatic relocation of clock network cells to preserve the placement of integrated clock gates during CTS. Setting to auto enables the automatic relocation feature | fc_shell> set_app_options -name cts.compile.enable_cell_relocation -value manual |
| 9 | compile.flow.enable_multibit | Enables multibit mapping. In the Fusion Compiler flow, clock gating works in conjunction with multibit register mapping, where the multibit packing ratio has higher precedence than clock gating. Clock-gating cells are not inserted to gate preinstantiated multibit registers | set_app_options -name compile.flow.enable_multibit -value true |
| 10 | compile.clockgate.physically_aw are | Controls placement-aware clock gating. The tool automatically disables this feature when clock-gate latency estimation is enabled, regardless of The option's setting | |
| 11 | compile.clockgate.physically_aw are | Enables placement-aware clock gating. When enabled, the tool replicates clock gates with timing-critical enables, adjusts clock gates so they are placed closer to their gated registers, and automatically annotates clock network latency for clock-gate cells | set_app_options -name compile.clockgate.physically_aware -value true |
| 12 | compile.flow.optimize_icgs | Enables or disables clock-gate optimization. Setting to false disables this optimization, which is recommended when using integrated clock-gate latency estimation | fc_shell> set_app_options -name compile.flow.optimize_icgs -value true |
| 13 | compile.clockgate.self_gating | Enables self-gating during the compile_fusion command. Self-gating gates registers with an enable condition that cannot be inferred from existing logic | set_app_options -name compile.clockgate.self_gating -value true |
| 14 | compile.flow.trial_clock_tree | Enables or disables trial clock tree synthesis. Setting to false disables trial clock tree synthesis, which is recommended when using integrated clock-gate latency estimation | fc_shell> set_app_options -name compile.flow.trial_clock_tree -value true |
| 15 | compile.clockgate.enable_dft_wr apper_cell_support | Enables clock gate support for DFT wrapper cells, allowing identification and special naming/querying of clock gates that drive wrapper cells during ATPG | set_app_options -name compile.clockgate.enable_dft_wrapper_cell_support -value true |
| 16 | opt.clock_latency_estimation.esti mate_smscts_subtrees | Ensures the tool estimates clock-gate latencies appropriate for structural multisource clock subtrees during integrated latency estimation. Must be set before running compile_fusion if planning structural multisource CTS | fc_shell> set_app_options -name opt.clock_latency_ estimation.estimate_smscts_subtrees -value true |
| 17 | compile.seqmap.honor_sync_set _reset | Controls whether the tool connects the reset signal as close to the register as possible when the library has registers with synchronous reset or preset pins. When set to true, the tool honors sync_set_reset RTL directives and connects reset signals close to the register data pin | |
| 18 | time.snapshot_storage_location | Sets the directory in which to store the quality information files generated by the create_qor_snapshot command. By default, snapshot files are stored in a directory named 'snapshot' under the current working directory | |
| 19 | hdlin.elaborate.ff_infer_async_se t_reset | Enables the tool to map to registers with asynchronous reset or preset signals during elaboration. When true (default), the tool infers asynchronous set/reset from RTL descriptions | |
| 20 | compile.flow.areaResynthesis | Enables the embedded area optimization flow during the logic_opto stage of compile_fusion. When enabled, performs dedicated ungrouping, fast area-driven logic restructuring, and light timing optimization before other optimization techniques. Reduces area of blocks with many DesignWare hierarchies | |
| 21 | compile.seqmap.remove_consta nt_registers | Controls whether the tool removes constant registers during optimization. When false, disables constant register removal for the entire block being synthesized | fc_shell> set_app_option -name compile.seqmap.remove_constant_registers -value true |
| 22 | multibit.naming.expanded_name _style | Sets the expanded naming styles for multibit registers created by combining elements of a multidimensional register array. See the man page for detailed information on allowed values | |
| 23 | compile.seqmap.remove_unload ed_registers | Controls whether the tool deletes registers whose outputs do not drive any load during optimization. When false, disables unloaded register removal for the block being synthesized | |
| 24 | compile.flow.enable_multibit | Enables the multibit banking flow. Must be set to true before running the create_multibit command on unmapped single-bit registers. When enabled, single-bit cells of a bus created by create_multibit are mapped into a multibit register bank during initial_map stage | fc_shell> set_app_option -name compile.flow.enable_multibit -value true |
| 25 | compile.flow.enable_toggle_awar e_rtl_multibit_reordering | Enables consideration of toggle rate when performing RTL-based multibit reordering at the logic_opto stage during compile_fusion | |
| 26 | opt.common.enable_multibit_feat ure | Enables site-aware debanking, clock useful skew (CUS), driver sizing, and early debanking of bottleneck multibit registers. Impacts debanking in initial_opto (compile_fusion), final_place, and final_opto (compile_fusion/place_opt) stages | |
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