| 1 | opt.common.advanced_logic_res tructuring_mode | Controls the advanced logic restructuring mode used during optimization. Shown being changed to timing between compile_fusion stages to influence optimization behavior | set_app_option -name opt.common.advanced_logic_restructuring_mode -value timing |
| 2 | shell.common.check_error_list | Sets the message IDs to query when using the check_error command. After setting The option, the check_error command can report whether any of the specified message IDs were issued during the previous command step | fc_shell> set_app_options -name shell.common.check_error_list -value {DES-001 CMD-005} |
| 3 | compile.optimization.enable_hier archical_inverter | Controls whether boundary optimization can move inverters across hierarchical boundaries (phase inversion). Set to false to prevent boundary optimization from moving inverters across hierarchical boundaries. Only effective when boundary optimization is enabled | set_app_options -name compile.optimization.enable_hierarchical_inverter -value true |
| 4 | time.snapshot_storage_location | Sets the directory where QoR snapshots created by create_qor_snapshot are stored. Used by remove_qor_snapshot to locate snapshots | |
| 5 | seqmap.bind_scan_pins | Used to hold the scan enable pin inactive when the tool maps sequential cells directly to scan registers in the library, where scan pins such as scan enable and scan out are unconnected | set_app_options -name seqmap.bind_scan_pins -value true |
| 6 | ccd.enable_top_wns_optimizatio n | Enables optimization of the worst 300 timing paths during targeted CCD optimization | fc_shell> set_app_options -name ccd.enable_top_wns_optimization -value true |
| 7 | hdlin.elaborate.ff_infer_sync_set _reset | Enables the tool to infer synchronous reset or preset flip-flops, or preserve the synchronous reset or preset logic close to the flip-flop, when the RTL does not contain the //synopsys sync_set_reset directive. Set to true to enable inference | set_app_options -name hdlin.elaborate.ff_infer_sync_set_reset -value true |
| 8 | ccd.targeted_ccd_end_points_fil e | Specifies a file containing the timing endpoints to target for targeted concurrent clock and data (CCD) optimization. Only the specified endpoints are optimized | fc_shell> set_app_options -name ccd.targeted_ccd_end_points_file -value endpoint_targets.tcl |
| 9 | compile.seqmap.identify_shift_re gisters | Controls whether the tool automatically identifies shift registers in the design during compile. When enabled, compile_fusion -to initial_opto maps the first register to a scan cell and the other cells to nonscan cells, improving sequential design area and reducing congestion. Set to false to disable this capability | set_app_options -name compile.seqmap.identify_shift_registers -value true |
| 10 | ccd.targeted_ccd_path_groups | Specifies path groups for which higher priority WNS optimization is applied during concurrent clock and data optimization | fc_shell> set_app_options -name ccd.targeted_ccd_path_groups -value {PG1 PG2} |
| 11 | compile.seqmap.enable_register _merging | Controls whether the tool performs register merging during optimization. By default the tool performs register merging. Set to false to disable register merging | set_app_options -name compile.seqmap.enable_register_merging -value true |
| 12 | ccd.dps.use_case | Customizes the power analysis performed during dynamic power shaping optimization | |
| 13 | opt.common.enable_multibit_co mbinational_cells | Enables combinational multibit mapping during the initial_opto and final_opto stages. Combinational multibit cells are library cells where a single cell implements multiple logic functions; the tool banks single-bit combinational cells to multibit combinational cells and debanks multibit combinational cells as needed to improve QoR | set_app_options -name opt.common.enable_multibit_combinational_cells -value true |
| 14 | compile.flow.enable_dps | Enables dynamic power shaping optimization to reduce dynamic voltage drop across a block during compile_fusion. Performed during the final_opto stage | fc_shell> set_app_options -name compile.flow.enable_dps -value true |
| 15 | compile.flow.enable_ccd | Controls whether the tool performs concurrent clock and data optimization during the compile_fusion command. Set to false to disable it. During CCD, the tool uses an ideal clock tree, updates clock latencies and balance points for all active scenarios, and adjusts register latencies within delayed and advanced latency settings for the most critical sequential elements | set_app_options -name compile.flow.enable_ccd -value true |
| 16 | ccd.optimize_boundary_timing | Enables or disables concurrent clock and data optimization for boundary timing paths (I/O paths and latencies for boundary registers) | fc_shell> set_app_options ccd.optimize_boundary_timing true |
| 17 | ccd.max_postpone | Specifies a maximum delayed latency for useful skew computation | set_app_options ccd.max_postpone 50 |
| 18 | ccd.skip_path_groups | Specifies one or more path groups for which useful skew computation is omitted during concurrent clock and data optimization | fc_shell> set_app_options ccd.skip_path_groups path_group_list |
| 19 | compile.flow.high_effort_timing | Enables high-effort timing mode for compile to achieve better timing QoR. The tool performs multiple passes of placement and optimization to obtain optimal timing results | set_app_options -name compile.flow.high_effort_timing -value 1 |
| 20 | ccd.max_prepone | Sets the maximum advanced latency (in ps) for useful skew computation in concurrent clock and data optimization | fc_shell> set_app_options ccd.max_prepone 100 |
| 21 | compile.flow.enhanced_delay_op to_for_pg | Enables enhanced delay optimization techniques that improve total negative slack. Has better runtime and better area and power QoR compared to the extensive use of path groups to improve total negative slack | set_app_options -name compile.flow.enhanced_delay_opto_for_pg -value 1 |
| 22 | compile.flow.enable_multibit | Enables multibit component mapping during compile. Required to view multibit components in the WordView GUI | fc_shell> set_app_options -name compile.flow.enable_multibit -value true |
| 23 | compile.flow.high_effort_area | Enables high-effort area mode for designs that need further reduction of area. The tool performs multiple passes of placement and optimization to obtain optimal area results | set_app_options -name compile.flow.high_effort_area -value true |
| 24 | compile.seqmap.prefer_registers _with_multibit_equivalent | During the initial_mapping stage, prioritizes use of sequential library cells that have functionally equivalent multibit library cells, to improve the banking ratio when many cells are not banked due to lack of multibit cells | |
| 25 | shell.synthesis.logic_level_report _summary_format | Sets the fields displayed in the summary section of the logic-level report generated by report_logic_levels. You can specify up to eight fields | set_app_options -name shell.synthesis.logic_level_report_summary_format -value "group num_paths max_level min_level avg_level" |
| 26 | multibit.naming.element_separat or_style | Controls the separator character used between bit indices for noncontiguous bits of a bused register in multibit optimization | |
| 27 | shell.synthesis.logic_level_report _group_format | Sets the fields displayed in the path group section of the logic-level report generated by report_logic_levels. You can specify up to ten fields | set_app_options -name shell.synthesis.logic_level_report_group_format -value "slack ll ll_buf_inv clockcycles startclk endclk" |
| 28 | multibit.naming.range_separator _style | Controls the separator character used between bit indices when naming contiguous bits of a bused register in multibit optimization | |
| 29 | place.coarse.handle_early_data | Allows placement to continue when a region is overutilized due to being too small or covered by blockages. Issues warning messages when utilization exceeds thresholds | set_app_options -name place.coarse.handle_early_data -value true |
| 30 | multibit.naming.compact_hierarc hical_name | When set to true, suppresses repetition of common hierarchical prefixes when forming multibit register names from hierarchical single-bit register names | |
| 31 | place.coarse.utilization_warning_ threshold | Changes the utilization warning threshold used when place.coarse.handle_early_data is enabled. The tool prints a warning message if utilization exceeds this threshold | |
| 32 | multibit.naming.name_prefix | Specifies a prefix string for multibit register names created during multibit optimization | |
| 33 | place.coarse.icg_auto_bound | Enables automatic generation of group bounds for integrated clock gating (ICG) cells and the sequential cells they drive. Bounds are created at the beginning of placement and removed at the end | fc_shell> set_app_options -name place.coarse.icg_auto_bound -value true |
| 34 | multibit.naming.multiple_name_s eparator_style | Controls the separator character used when concatenating single-bit register names to form a multibit register name | |
| 35 | place.coarse.icg_auto_bound_fa nout_limit | Limits the maximum number of fanouts that can be included in an automatic ICG group bound | fc_shell> set_app_options -name place.coarse.icg_auto_bound_fanout_limit -value 30 |
| 36 | compile.flow.enable_multibit_rew iring | Enables multibit register rewiring for the compile_fusion command | set_app_options -name compile.flow.enable_multibit_rewiring -value true |
| 37 | place.coarse.auto_density_contr ol | Controls automatic density scheduling during placement. When enabled (default -enhanced), the tool follows a preset schedule during the flow. Disabling it or manually setting place.coarse.max_density to 0 causes uniform spreading of cells in the core area | |
| 38 | multibit.common.exclude_size_o nly_cells | Includes cells with user-specified size_only settings during physical banking and debanking when set to false | set_app_options -name multibit.common.exclude_size_only_cells -value true |
| 39 | place.coarse.max_density | Specifies a maximum density that controls how densely the tool can place cells during non-congestion-driven placement. Choose a value between 1 and the overall utilization of the block | fc_shell> set_app_options -name place.coarse.max_density -value 0.6 |
| 40 | mv.cells.enable_multibit_pm_cell s | Enables timing-driven banking of power management cells; skips fixed cells and cells with dont_touch, legalize_only, or size_only attributes | set_app_options -name mv.cells.enable_multibit_pm_cells -value true |
| 41 | place.coarse.congestion_driven_ max_util | Specifies a maximum utilization that controls how densely the tool can place cells in less congested areas surrounding highly congested areas, so cells in congested areas can spread out to reduce congestion | fc_shell> set_app_options -name place.coarse.congestion_driven_max_util -value 0.8 |
| 42 | multibit.banking.across_equivale nt_icg | Enables banking of registers driven by equivalent integrated-clock-gating (ICG) cells | set_app_options -name multibit.banking.across_equivalent_icg -value true |
| 43 | place.coarse.cong_restruct_effor t | Sets the effort level for congestion-driven restructuring during placement. The tool restructures nets to reduce congestion during create_placement (except with -timing_driven) and the initial_place stage of compile_fusion | |
| 44 | multibit.banking.lcs_consider_mu lti_si_cells | Considers multibit register library cells with multiple scan-in pins and internal scan-in pins during banking | set_app_options -name multibit.banking.lcs_consider_multi_si_cells -value true |
| 45 | place.coarse.cong_restruct_dept h_aware | Prevents the tool from increasing the path depth by more than three levels of logic during congestion-driven restructuring | |
| 46 | multibit.banking.enable_strict_sc an_check | Ignores scan flip-flops not included in SCANDEF information during banking | set_app_options -name multibit.banking.enable_strict_scan_check -value true |
| 47 | place.coarse.congestion_layer_a ware | Enables the tool to consider the congestion of each layer separately to improve accuracy of congestion reduction in coarse placement. Helps identify and fix areas with high pin densities with insufficient resources on lower layers | |
| 48 | compile.flow.enable_multibit_deb anking | Enables splitting of multibit register banks when it improves total negative slack (TNS), during initial_opto and final_opto stages | fc_shell> set_app_options -name compile.flow.enable_multibit_debanking -value true |
| 49 | place.coarse.increased_cell_exp ansion | Expands the virtual area of cells during placement based on local routing resource needs. Minimizes cell density and congestion in areas with shortage of routing resources | |
| 50 | compile.flow.enable_second_pas s_multibit_banking | Enables placement-based multibit banking during the final_place stage instead of initial_opto stage | fc_shell> set_app_options -name compile.flow.enable_second_pass_multibit_banking -value true |
| 51 | place.coarse.congestion_expansi on_direction | Controls the direction in which the tool expands cell virtual areas during placement. For designs with congestion mainly in horizontal routing layers, set to both | |
| 52 | compile.flow.enable_physical_m ultibit_banking | Enables placement-based multibit register banking during the initial_opto stage of compile_fusion | fc_shell> set_app_options -name compile.flow.enable_physical_multibit_banking -value true |
| 53 | route.global.export_soft_congesti on_maps | Enables the tool to consider the congestion effects of soft routing rules when using the global route congestion map to identify highly congested areas for cell expansion during placement | |
| 54 | compile.flow.enable_rtl_multibit_ debanking | Enables splitting of RTL-level multibit register banks when registers are on critical timing paths during the logic_opto stage | fc_shell> set_app_options -name compile.flow.enable_rtl_multibit_debanking -value true |
| 55 | place.coarse.wide_cell_use_mod el | Enables wide-cell modeling during placement for advanced technology nodes. Minimizes density of wide cells (wider than half the pitch of power straps) to ensure they can be placed and legalized without large displacements | |
| 56 | compile.flow.enable_rtl_multibit_ banking | Enables combining single registers or smaller register banks at the RTL level into larger banks during the initial_map stage | fc_shell> set_app_options -name compile.flow.enable_rtl_multibit_banking -value true |
| 57 | place.coarse.pin_cost_aware | Specifies that the tool uses a technology-specific pin-cost model during placement to improve pin accessibility. During placement, the tool tries to improve pin accessibility using a technology-specific model to predict routing resources required to access each pin | |
| 58 | compile.flow.enable_multibit | Enables integrated multibit register optimization during the compile_fusion command | fc_shell> set_app_options -name compile.flow.enable_multibit -value true |
| 59 | place.coarse.pin_density_aware | Controls the maximum local pin density during placement for all technology nodes other than 7, 7+, 5, s5, or s4 | |
| 60 | compile.initial_drc.global_route_ based | Enables the use of globally routed nets to determine the topology for buffers inserted during high-fanout synthesis, during the initial_drc stage of the compile_fusion command. Benefits designs with high congestion in routing channels. Increases compile_fusion runtime | fc_shell> set_app_options -name compile.initial_drc.global_route_based -value true |
| 61 | place.coarse.ndr_area_aware | Enables the tool to consider the effects of nondefault routing rules of clock nets during placement. Nondefault routing rules require additional space and can increase congestion after clock routing | |
| 62 | compile.seqmap.print_cross_pro bing_info_for_removed_registers | When set to true, prints the RTL file name and line number of registers optimized (removed/merged) during compile_fusion in the log file and in report_transformed_registers output | fc_shell> set_app_options -name compile.seqmap.pr int_cross_probing_info_for_removed_registers -value true |
| 63 | place.coarse.seq_array_icg_awa re | Enables the tool to consider the clock-gating cells of sequential arrays during placement. A sequential array is a group of registers arranged as a 2D array; their clock pins are driven by a single clock-gating cell. Enabling reduces congestion caused by clock nets | |
| 64 | compile.seqmap.remove_unload ed_registers | Controls global removal of unloaded registers during compile. When set to false, disables unloaded register removal for the entire block. Can be overridden per-module using set_unloaded_register_removal | fc_shell> set_app_option -name compile.seqmap.remove_unloaded_registers -value true |
| 65 | place.coarse.enhanced_legalizer _driven_placement | Enables the tool to be aware of legalization limits and restrictions during coarse placement, minimizing cells displaced during legalization. For example, prevents placing a wide cell where power straps restrict legalization | |
| 66 | compile.seqmap.disable_qn_usa ge | Prevents the tool from using the QN pin of registers during sequential mapping. By default, the tool may map registers to library cells with both Q and QN pins if doing so improves QoR | |
| 67 | place.coarse.enable_dft_modelin g | Improves DFT logic placement by enhancing the tool's awareness of DFT connectivity while still optimizing for functional placement | |
| 68 | compile.seqmap.enable_output_i nversion | Controls sequential output inversion for the entire block. When enabled, the compile_fusion command allows mapping of sequential elements to library cells whose output phase is inverted. An instance-specific setting via set_register_output_inversion overrides this block-level setting | |
| 69 | place.coarse.enhanced_low_pow er_effort | Enables dynamic-power-driven placement for the create_placement, refine_placement, compile_fusion, or clock_opt command. During dynamic-power-driven placement, the tool tries to improve both timing and power of timing-critical nets and power of other nets | |
| 70 | compile.seqmap.exact_map | Specifies that the tool maps sequential elements exactly as described in the RTL. Disables mapping to sequential library cells with inverted outputs or unused ports | set_app_options -name compile.seqmap.exact_map -value true |
| 71 | place.coarse.ir_drop_aware | Enables IR-drop-aware placement. The tool uses voltage (IR) drop values of cells to identify areas of high power density and spreads cells with high voltage drop values, reducing power density | |
| 72 | compile.datapath.ungroup | Controls whether DesignWare cells and datapath blocks are ungrouped during timing optimization. By default all such cells are ungrouped; setting to false disables ungrouping | fc_shell> set_app_options -name compile.datapath.ungroup -value true |
| 73 | place.coarse.ir_drop_aware | When set to true, enables IR-drop-aware placement. The tool creates three categories of cells based on total number of cells: upper (top 1% highest voltage drop - spread most), middle (next 5% - spread less), lower (rest - not spread) | |
| 74 | compile.flow.constant_and_unloa ded_propagation_with_no_boun dary_opt | Controls whether constant and unloaded propagation occurs across hierarchies when boundary optimization is disabled. Setting to false disables both constant and unloaded propagation globally | fc_shell> set_app_options -name compile.flow.const ant_and_unloaded_propagation_with_no_boundary_ opt -value true |
| 75 | opt.common.advanced_logic_res tructuring_wirelength_costing | Controls whether the tool accepts logic restructuring results that increase wire length. For designs without congestion or routing issues, setting to medium or none allows the tool to accept restructuring even if it increases wire length | |
| 76 | compile.flow.boundary_optimizati on | Controls boundary optimization globally during compile. When set to false, disables propagation of equal-opposite logic and phase inversion; constants and unloaded ports continue to propagate | fc_shell> set_app_options -name compile.flow.boundary_optimization -value true |
| 77 | power.use_generated_clock_sca ling_factor | Enables scaling of switching activity when the clock frequency used in the SAIF file differs from the clock frequency used in Fusion Compiler. Must be enabled before using set_power_clock_scaling command | |
| 78 | compile.flow.autoungroup | Controls whether the compile_fusion command automatically ungroups logical hierarchies that do not have a dont_touch attribute. Ungrouping removes hierarchical boundaries to improve timing by reducing logic levels and improve area by sharing logic | |
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