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INNOVUS APP OPTIONS

Self-Gating and Multi-Source CTS

S.NoApp OptionDescriptionExample
1compile.clockgate.self_gatingEnables self-gating optimization during compile_fusion; inserts self-gating logic to reduce dynamic power based on SAIF switching activityset_app_options -name compile.clockgate.self_gating -value true
2cts.multisource.subtree_split_cell _name_prefixSpecifies name prefix to use when splitting clock cells during multisource clock tap assignmentset_app_options -name cts.multisource.subtree_split_cell_name_prefix -value
3compile.clockgate.substring_list_ for_dft_wrapper_dont_rename_ic gsRestricts the renaming of pre-existing clock gates that drive wrapper cells only. Clock gates whose names match any substring in this list are not renamed during the DFT wrapper clock gate naming flowset_app_options -name compile.clockgate.substring _list_for_dft_wrapper_dont_rename_icgs -value {clk_gate_ctl clk_gate_snps}
4cts.multisource.subtree_merge_c ell_name_suffixSpecifies name suffix to use when merging clock cells during multisource clock tap assignmentset_app_options -name cts.multisource.subtree_merge_cell_name_suffix -value
5cts.common.enable_dirty_design _modeEnables dirty design mode for clock tree synthesis so that CTS produces usable results in reasonable runtime when constraints are inaccurate or too restrictive. The tool ignores dont_touch/dont_touch_network on clock nets, removes too-tight max transition and max capacitance constraints, removes max net length constraints under 50 microns, ignores overly strict clock cell spacing rules and nondefault routing rules, and reports large balance point delay valuesset_app_options -name cts.common.enable_dirty_design_mode -value true
6cts.multisource.subtree_merge_c ell_name_prefixSpecifies name prefix to use when merging clock cells during multisource clock tap assignmentset_app_options -name cts.multisource.subtree_merge_cell_name_prefix -value
7clock_opt.flow.enable_clock_pow er_recoveryEnables clock power recovery (or area recovery) on clock cells and registers when concurrent clock and data optimization is not used. Set to 'power' to enable power recovery during clock_opt; set to 'area' to enable area recovery on the clock cells and registers during the final_opt stage of clock_optset_app_options -name clock_opt.flow.enable_clock_power_recovery -value power
8cts.multisource.tap_selectionSets the configuration strategy for tap drivers in multisource clock trees. When set to symmetric, the tool derives a symmetric tap driver configurationfc_shell> set_app_options -name cts.multisource.tap_selection -value symmetric
9place.coarse.ir_drop_awareEnables IR-drop-aware placement so the tool uses voltage (IR) drop values of cells to identify areas of high power density and spreads cells with high voltage drop values, reducing power density of such areasset_app_options -name place.coarse.ir_drop_aware -value true
10cts.multisource.flexible_htree_sy nthesisEnables flexible H-tree synthesis for multisource clock trees. When enabled, the tool identifies the best count, configuration, and placement of tap drivers to minimize clock tree insertion delayfc_shell> set_app_options -name cts.multisource.flexible_htree_synthesis -value true
11est_delay.ml_delay_opto_dirSets the output directory for the machine learning data used to improve correlation during global-route-based optimizationset_application_option -name est_delay.ml_delay_opto_dir -value ./ML
12cts.multisource.enable_mlph_flo wEnables clock driver insertion for multiple levels of physical hierarchy. When enabled, the create_clock_drivers command can insert clock drivers from the top level into lower-level physical blocks
13est_delay.ml_delay_gre_modeEnables the machine learning model, derived in the previous iteration, during global-route-based optimizationset_application_option -name est_delay.ml_delay_gre_mode -value enable
14cts.multisource.enable_mlph_flo wEnables clock driver insertion for designs with multiple levels of physical hierarchy when set to true
15cts.multisource.enable_full_mv_s upportEnables multivoltage support for multisource clock tree implementation in multivoltage designsset_app_options -name cts.multisource.enable_full_mv_support -value true
16cts.multisource.enable_pin_acce ssibility_for_global_clock_treesControls whether the create_clock_drivers command creates temporary placement blockages for preroutes on routing layers used for H-trees. Setting to false prevents these temporary blockages, which may be needed when multirow-height cells cannot be placed due to blockages
17opt.common.allow_physical_feed throughEnables the addition of physical feedthrough cells, which belong to a voltage area physically but not logicallyset_app_options -name opt.common.allow_physical_feedthrough -value true
18cts.multisource.enable_clock_dri ver_snappingSpecifies that inserted clock drivers should be aligned with the clock straps of the mesh structure during multisource CTSset_app_options -name cts.multisource.enable_clock_driver_snapping -value true
19cts.multisource.cell_em_awareEnables cell electromigration fixing during multisource clock tree implementationset_app_options -name cts.multisource.cell_em_aware -value true
20cts.multisource.enable_subtree_ synthesis_aware_ccdEnables improved correlation between structural multisource clock tree synthesis (SMSCTS) and concurrent clock and data (CCD) optimization by using enhanced CCD engine with more SMSCTS-specific offsets. Improves CCD balance point implementation and timing after SMSCTS
21cts.multisource.subtree_routing_ modeControls the routing mode used for local clock subtree synthesis. By default the tool global routes the nets; setting it to fishbone creates a mix of detail routed fishbone trunks and fingers, with global comb routes connecting the net loads to the fishbone fingersset_app_options -name cts.multisource.subtree_routing_mode -value fishbone
22clock_opt.flow.enable_multisourc e_clock_treesEnables integrated structural multisource clock tree synthesis during clock_opt -from build_clock -to route_clock to synthesize entire clock tree from root and incrementally optimize existing subtreesfc_shell> set_app_options -name clock_opt.flow.enable_multisource_clock_trees -value true
23cts.multisource.subtree_merge_c ell_name_prefixSets the name prefix to use when merging clock cells during local subtree synthesis
24compile.flow.enable_multisource _clock_treesEnables integrated structural multisource clock tree synthesis when running compile_fusion -from initial_placefc_shell> set_app_options -name compile_flow.flow.enable_multisource_clock_trees -value true
25cts.multisource.subtree_merge_c ell_name_suffixSets the name suffix to use when merging clock cells during local subtree synthesis
26compile.flow.enable_multisource _clock_treesEnables integrated structural multisource clock tree synthesis when running compile_fusion -from initial_place to build local subtreesfc_shell> set_app_options -name compile_flow.flow.enable_multisource_clock_trees -value true
27cts.multisource.subtree_split_cell _name_prefixSets the name prefix to use when splitting clock cells during local subtree synthesis
28cts.multisource.cell_em_awareEnables cell electromigration (EM) fixing during multisource clock tree synthesisfc_shell> set_app_options -name cts.multisource.cell_em_aware -value true
29cts.multisource.subtree_split_cell _name_suffixSets the name suffix to use when splitting clock cells during local subtree synthesis
30cts.multisource.enable_multi_cor ner_supportEnables multicorner optimization during multisource CTS; tool considers all corners associated with the modefc_shell> set_app_options -name cts.multisource.enable_multi_corner_support -value true
31cts.multisource.subtree_split_net _name_prefixSets the name prefix to use for nets created when splitting clock cells during local subtree synthesis
32opt.common.allow_physical_feed throughEnables the addition of physical feedthrough cells, which belong to a voltage area physically but not logicallyfc_shell> set_app_options -name opt.common.allow_physical_feedthrough -value true
33cts.multisource.subtree_split_net _name_suffixSets the name suffix to use for nets created when splitting clock cells during local subtree synthesis
34cts.multisource.enable_full_mv_s upportEnables full multivoltage support for multisource clock tree synthesisfc_shell> set_app_options -name cts.multisource.enable_full_mv_support -value true
35cts.routing.fishbone_max_tie_dis tanceControls the maximum tie distance used during fishbone routing of clock subtrees
36cts.multisource.cell_em_awareEnables cell electromigration (EM) fixing during structural multisource clock tree implementation
37cts.routing.fishbone_max_sub_ti e_distanceControls the maximum sub-tie distance used during fishbone routing of clock subtrees
38opt.common.allow_physical_feed throughEnables the addition of physical feedthrough cells, which belong to a voltage area physically but not logically, for multivoltage structural multisource clock tree designsfc_shell> set_app_options -name opt.common.allow_physical_feedthrough -value true
39cts.routing.fishbone_bias_thresh oldControls the bias threshold used during fishbone routing of clock subtrees
40cts.multisource.enable_full_mv_s upportEnables multivoltage support for structural multisource clock tree implementationfc_shell> set_app_options -name cts.multisource.enable_full_mv_support -value true
41cts.routing.fishbone_bias_windo wControls the bias window used during fishbone routing of clock subtrees
42cts.multisource.power_aware_fle xible_htree_synthesisEnables power-aware flexible H-tree synthesis. When enabled, the tool estimates latency and power for each subtree configuration, tabulates results, and determines the best solution for power-aware flexible H-tree synthesisfc_shell> set_app_options -name cts.multisource.po wer_aware_flexible_htree_synthesis -value true
43cts.routing.fishbone_horizontal_b ias_spacingControls the horizontal bias spacing used during fishbone routing of clock subtrees
44cts.multisource.cell_em_awareEnables cell electromigration fixing during multisource clock tree synthesisfc_shell> set_app_options -name cts.multisource.cell_em_aware -value true
45cts.routing.fishbone_vertical_bias _spacingControls the vertical bias spacing used during fishbone routing of clock subtrees
46opt.common.allow_physical_feed throughEnables the addition of physical feedthrough cells, which belong to a voltage area physically but not logically. Required for multivoltage multisource CTS flowsfc_shell> set_app_options -name opt.common.allow_physical_feedthrough -value true
47compile.clockgate.fanin_sequenti alEnables fanin-based sequential clock gating. When enabled, a register can be gated during a given clock cycle if all registers in the transitive fanin did not change state in the previous clock cycleset_app_options -name compile.clockgate.fanin_sequential -value true
48cts.multisource.enable_full_mv_s upportEnables full multivoltage support for multisource clock tree synthesis. Required step for multivoltage designs before running multisource CTSfc_shell> set_app_options -name cts.multisource.enable_full_mv_support -value true
49cts.common.enable_auto_except ionsEnables automatic detection of endpoints with balancing conflicts and derivation of ignore pins to resolve the conflict. This capability is enabled by default for the synthesize_clock_trees and clock_opt commands
50compile.flow.enable_multisource _clock_treesEnables integrated tap assignment for multisource clock tree synthesis when running compile_fusion -from initial_placefc_shell> set_app_options -name compile_flow.flow.enable_multisource_clock_trees -value true
51opt.common.enable_target_librar y_subset_optEnables use of the target library subset during clock tree synthesis and optimization. Must be set to 1 to activate set_target_library_subset -clock restrictionsfc_shell> set_app_options -name opt.common.enable_target_library_subset_opt -value 1
52cts.multisource.cell_em_awareEnables cell electromigration (EM) fixing during multisource clock tree synthesis
53cts.compile.enable_local_skewEnables local skew optimization during the clock tree synthesis stage (synthesize_clock_trees command). Local skew optimizes the worst skew between launch and capture registers of timing paths, improving timing QoR compared to global skew minimizationfc_shell> set_app_options -list {cts.compile.enable_local_skew true}
54opt.common.allow_physical_feed throughEnables the addition of physical feedthrough cells that belong to a voltage area physically but not logically, required for multivoltage multisource CTS
55cts.optimize.enable_local_skewEnables local skew optimization during the clock tree optimization stage (clock_opt command). Works on improving local skew of all violating setup and hold timing pathsfc_shell> set_app_options -list {cts.optimize.enable_local_skew true}
56cts.multisource.enable_full_mv_s upportEnables multivoltage support for multisource clock tree synthesis in multivoltage designs
57cts.common.enable_auto_skew_ target_for_local_skewControls whether the tool automatically derives skew targets for local skew. When set to false, prevents the tool from deriving skew targets automaticallyset_app_options -name cts.common.enable_auto_sk ew_target_for_local_skew -value true
58opt.common.enable_via_ladder_i nsertionEnables high-performance and electromigration via ladder insertion for critical paths during the clock_opt command. Via ladders are stacked vias starting from the pin layer extending into an upper layer where the router connects, reducing via resistance to improve performance and electromigration robustness
59cts.compile.primary_cornerIdentifies a specific corner as the primary corner for initial clock tree synthesis. By default, the tool identifies the corner with the worst clock delaysset_app_options -name cts.compile.primary_corner -value
60est_delay.ml_delay_gre_modeEnables integrated ML feature extraction during global-route-based optimization. Set to 'feature' to enable feature extraction in build_clock/route_clock stagesset_application_option -name est_delay.ml_delay_gre_mode -value feature
61cts.common.skip_cts_clocksSpecifies clocks to prevent from being synthesized during CTS. By default, the tool synthesizes all clocks defined with create_clock and create_generated_clock commandsset_app_options -name cts.common.skip_cts_clocks -value CK_B
62est_delay.ml_delay_opto_dirSets the output directory for machine learning data used in global-route-based optimization after CTS. ML features and labels are written to this directoryset_application_option -name est_delay.ml_delay_opto_dir -value ./ML
63cts.compile.remove_existing_clo ck_treesControls whether the tool removes all preexisting clock buffers and inverters when performing clock tree synthesis. Set to false to preserve preexisting clock treesset_app_options -name cts.compile.remove_existing_clock_trees -value true
64ccd.skew_opt_merge_dcg_cells_ by_driverEnhances concurrent clock and data optimization to skew latches and discrete clock gating elements by the same offset, ensuring the latch and gate are at the same level and improving hold timing of discrete clock gatesfc_shell> set_attribute -name ccd.skew_opt_merge_dcg_cells_by_driver -value true
65cts.compile.power_opt_modeEnables clock tree power reduction techniques. gate_relocation relocates clock-gating cells closer to their drivers; low_power_targets uses clustering techniques; all uses both techniquesset_app_options -name cts.compile.power_opt_mode -value gate_relocation
66ccd.post_route_buffer_removalEnables removal of buffers or pairs of inverters during concurrent clock and data optimization performed at the postroute stage (route_opt) to improve QoRfc_shell> set_app_options -name ccd.post_route_buffer_removal -value true
67cts.compile.power_opt_modeEnables wire length aware activity-driven clock gate relocation. Setting to all or gate_relocation enables activity-driven clock gate relocation that controls wire length degradation and considers power impact. Clock gates are not relocated if relocation has minor power benefit, degrades power while degrading wire length, or has significant wire length impact for less power benefitset_app_options -name cts.compile.power_opt_mode -value selected
68route_opt.flow.enable_ccdEnables concurrent clock and data (CCD) optimization during the route_opt commandfc_shell> set_app_options -name route_opt.flow.enable_ccd -value true
69cts.placement.cell_spacing_rule_ styleControls how spacing rules between adjoining clock cells are computed. When set to 'maximum', uses the larger of two adjoining cell spacing values instead of summing themset_app_options -name cts.placement.cell_spacing_rule_style -value maximum
70ccd.targeted_ccd_wns_optimizati on_effortSets the effort level for worst negative slack (WNS) optimization during targeted CCD optimizationset_app_options -name ccd.targeted_ccd_wns_optimization_effort -value medium
71cts.common.user_instance_nam e_prefixSpecifies a name prefix for the cells added on the clock network during clock tree synthesisfc_shell> set_app_options -name cts.common.user_instance_name_prefix -value "CTS_"
72ccd.targeted_ccd_select_optimiz ation_movesSets the type of optimization moves performed during targeted concurrent clock and data (CCD) optimizationset_app_options -name ccd.targeted_ccd_select_optimization_moves -value size_only
73cts.compile.global_route_aware_ bufferingEnables the global router during the initial clock tree synthesis stage of the synthesize_clock_trees and clock_opt commands. By default initial CTS uses the virtual router; enabling The option reduces congestion hotspots and improves clock QoR for designs with complex floorplansfc_shell> set_app_options -name cts.compile.global_route_aware_buffering -value true
74ccd.targeted_ccd_end_points_fil eSpecifies a file containing the endpoints to target for targeted CCD WNS optimizationset_app_options -name ccd.targeted_ccd_end_points_file -value clkA_ep.txt
75cts.icg.latency_driven_cloningEnables level-driven clock-gate (CG) splitting. When enabled, the tool automatically identifies and evaluates different CG cloning moves to improve clock insertion delay to meet the maximum level constraint
76ccd.targeted_ccd_path_groupsSpecifies path groups targeted for WNS optimization during targeted CCDset_app_options -name ccd.targeted_ccd_path_groups -value clkA
77cts.buffering.reduce_clock_level_ effortControls the effort level for clock level improvement during clock tree building. When set to high, the tool considers level improvement as a metric while building clock trees and considers buffering solutions to improve repeater levels, resulting in fewer buffer trees chosen and local level improvement
78route_opt.flow.enable_targeted_ ccd_wns_optimizationEnables targeted concurrent clock and data WNS optimization during the route_opt commandset_app_options -name route_opt.flow.enable_target ed_ccd_wns_optimization -value true
79cts.optimize.enable_congestion_ aware_ndr_promotionEnables congestion-aware nondefault routing rule (NDR) promotion during clock tree synthesis. The tool derives new NDR spacing requirements based on existing routing rules to reduce congestionfc_shell> set_app_options -name cts.optimize.enabl e_congestion_aware_ndr_promotion -value true
80route_opt.flow.enable_ccdEnables regular concurrent clock and data optimization during the route_opt commandset_app_options -name route_opt.flow.enable_ccd -value true
81cts.compile.timing_driven_sink_tr ansitionEnables timing driven sink transition target for clock tree synthesis. The tool applies a transition target tighter than the user-specified max_transition for clock pins of timing-critical endpoints, building the clock tree with tightened transition to improve timingfc_shell> set_app_options -name cts.compile.timing_driven_sink_transition -value true
82ccd.targeted_ccd_threshold_for_ nontargeted_path_groupsThreshold beyond which the slack for non-targeted path groups can be degraded during targeted CCD WNS optimization- (referenced by name only on this page)
83clock_opt.flow.enable_voltage_dr op_awareEnables voltage-drop-aware clock tree synthesis using RedHawk Fusion PG network analysis results loaded via open_rail_resultfc_shell> set_app_options -name clock_opt.flow.enable_voltage_drop_aware -value true
84ccd.targeted_ccd_wns_optimizati on_effortSpecifies optimization effort for targeted concurrent clock and data WNS optimization. Higher effort improves QoR for targeted paths at the expense of non-targeted paths- (referenced by name only on this page)
85clock_opt.flow.optimize_ndrEnables use of nondefault routing rules on timing-critical nets during preroute optimization to improve timing QoRfc_shell> set_app_options -name clock_opt.flow.optimize_ndr -value true
86ccd.skip_path_groupsSpecifies path groups to skip during concurrent clock and data optimization
87clock_opt.flow.enable_ccdEnables concurrent clock and data (CCD) optimization during the clock_opt command; adjusts clock arrival times of registers using positive slackfc_shell> set_app_options -name clock_opt.flow.enable_ccd -value true
88ccd.targeted_ccd_select_optimiz ation_movesSets the type of optimization moves to perform during targeted concurrent clock and data optimization
89clock_opt.flow.enable_multibit_re wiringEnables rewiring of mixed-drive-strength multibit cells during the clock_opt command. When enabled, if a violating path goes through a lower-drive-strength bit, the tool rewires the mixed-drive-strength multibit cell so the violating path goes through a higher-drive-strength bitfc_shell> set_app_options -name clock_opt.flow.enable_multibit_rewiring -value true
90ccd.targeted_ccd_path_groupsSpecifies path groups to optimize during targeted concurrent clock and data optimization at the postroute stage
91clock_opt.flow.enable_multibit_d ebankingEnables debanking of multibit registers during the final_opt stage of the clock_opt command to improve timing QoR, provided debanking does not introduce hold timing violationsfc_shell> set_app_options -name clock_opt.flow.enable_multibit_debanking -value true
92route_opt.flow.enable_targeted_ ccd_wns_optimizationEnables targeted concurrent clock and data (CCD) optimization for the route_opt command at the postroute stage
93route_opt.flow.enable_ccdEnables concurrent clock and data (CCD) optimization for the route_opt command. CCD applies useful skew techniques during datapath optimization to improve timing QoR by taking advantage of positive slack and adjusting clock arrival times of registers. CCD is enabled by default for compile_fusion and clock_opt, but must be explicitly enabled for route_optfc_shell> set_app_options -name route_opt.flow.enable_ccd -value true
94ccd.enable_top_wns_optimizatio nEnables optimization of the worst 300 timing paths during concurrent clock and data optimization
95ccd.max_preponeLimits the amount that clock latencies can be advanced during concurrent clock and data optimization performed by place_opt, clock_opt, and route_optfc_shell> set_app_options -list {ccd.max_prepone 0.2}
96ccd.targeted_ccd_end_points_fil eSpecifies a file containing specific endpoints for targeted concurrent clock and data (CCD) optimization at clock_opt or route_opt stagefc_shell> set_app_options -name ccd.targeted_ccd_end_points_file -value endpoint_targets.tcl
97ccd.max_postponeLimits the amount that clock latencies can be delayed during concurrent clock and data optimizationfc_shell> set_app_options -list {ccd.max_postpone 0.1}
98ccd.targeted_ccd_path_groupsSpecifies path groups to give higher priority to WNS optimization when performing concurrent clock and data optimization using place_opt or clock_opt commandsfc_shell> set_app_options -name ccd.targeted_ccd_path_groups -value {PG1 PG2}
99ccd.optimize_boundary_timingControls whether concurrent clock and data optimization is performed on boundary paths (registers in transitive fanout of input ports and fanin of output ports)fc_shell> set_app_options -name ccd.optimize_boundary_timing -value true
100route_opt.flow.enable_irdrivenoptEnables IR-driven sizing, which uses RedHawk dynamic voltage drop analysis results to identify cells involved in voltage drop violations and replaces them with cells having smaller leakage current
101ccd.ignore_ports_for_boundary_i dentificationSpecifies ports whose boundary paths should be ignored during boundary path exclusion, allowing CCD optimization on those specific boundary pathsfc_shell> set_app_options -name ccd.ignore_ports_for_boundary_identification -value {IN_A OUT_A}
102ccd.voltage_drop_population_thr esholdSpecifies a threshold for the number of cells as a percentage of total cells. Cells are selected for voltage-drop optimization starting with the worst violator
103ccd.optimize_boundary_timing_u pstreamControls whether the clock tree fanin cone of boundary registers can be modified during CCD optimization; setting to false prevents clock tree fanin changes for boundary registersset_app_options -name ccd.optimize_boundary_timing_upstream -value true
104ccd.voltage_drop_voltage_thresh oldSpecifies a threshold for cell voltage drop as a percentage of the supply voltage. Cells with voltage drop exceeding this threshold are selected for voltage-drop optimization
105ccd.skip_path_groupsSpecifies path groups to exclude from concurrent clock and data (CCD) optimization. Can exclude a group globally or only for a specific scenariofc_shell> set_app_options -name ccd.skip_path_groups -value {CLK1 {CLK2 scnA}}
106route_opt.flow.enable_voltage_dr op_opt_ccdEnables dynamic-voltage-drop-driven concurrent clock and data optimization during the route_opt command. Uses RedHawk Fusion to identify voltage drop hotspots and relocate cells to reduce peak dynamic voltage drop without affecting timing QoR
107ccd.ignore_scenariosSpecifies scenarios to exclude from concurrent clock and data (CCD) optimizationfc_shell> set_app_options -name ccd.ignore_scenarios -value {scnB}
108ccd.skip_path_groupsSpecifies path groups to exclude from concurrent clock and data optimization. Excluding a path group also prevents I/O clock latency updates for the corresponding I/O pathsfc_shell> set_app_options -name ccd.skip_path_groups -value {group1 group2}
109ccd.respect_cts_fixed_balance_p insWhen set to true, prevents CCD optimization from adjusting latencies of sinks that have the cts_fixed_balance_pin attribute set to true
110ccd.optimize_boundary_timingControls whether concurrent clock and data optimization is applied to boundary paths. Disabling prevents I/O clock latency updates and boundary path CCD optimizationfc_shell> set_app_options -name ccd.optimize_boundary_timing -value true
111ccd.respect_cts_fixed_balance_p insControls how CCD optimization respects CTS fixed balance pins. Setting to 'upstream' instead of 'true' changes the behavior during concurrent clock and data optimizationfc_shell> set_app_options -name ccd.respect_cts_fixed_balance_pins -value upstream
112ccd.adjust_io_clock_latencyControls whether the tool adjusts the latencies of I/O clocks (clocks constraining boundary ports) during CCD optimization in clock_opt. When disabled, the tool does not update I/O clock latencies for the entire blockfc_shell> set_app_options -name ccd.adjust_io_clock_latency -value true
113ccd.timing_effortControls the effort level for timing optimization during concurrent clock and data optimization. The tool focuses on improving timing and power QoR by defaultfc_shell> set_app_options -name ccd.timing_effort -value maximum
114ccd.hold_control_effortControls the effort for hold timing fixing during concurrent clock and data optimization. Increasing hold priority reduces the number of setup violations that are fixedfc_shell> set_app_options -name ccd.hold_control_effort -value medium

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