| 1 | setMultiCpuUsage -releaseLicense | Releases multi-CPU licenses at the point The command is called, for example after global placement finishes | setMultiCpuUsage -releaseLicense |
| 2 | setMetalFill -maxLength | Sets the maximum length for inserted metal fill shapes | setMetalFill -activeSpacing value -gapSpacing value -maxWidth value -maxLength value -windowSize x y -windowStep x_step y_step -minDensity value -maxDensity value |
| 3 | setMultiCpuUsage -threadInfo | Sets the level of thread usage information written to the log file. 0=no thread info, 1=write final message, 2=write starting/ending information for each thread | setMultiCpuUsage -threadInfo 2 |
| 4 | setMetalFill -maxWidth | Sets the maximum width for inserted metal fill shapes | setMetalFill -activeSpacing value -gapSpacing value -maxWidth value -maxLength value -windowSize x y -windowStep x_step y_step -minDensity value -maxDensity value |
| 5 | setOptMode -opt_power_effort | Sets the effort level for power optimization. For designs where leakage is a high priority, enables leakage optimization at the beginning of the flow | setOptMode -opt_power_effort {minimal | maximum} -opt_leakage_to_dynamic_ratio 0.8 |
| 6 | setMetalFill -gapSpacing | Sets the gap spacing rule for metal fill, controlling the minimum distance between metal fill shapes | setMetalFill -activeSpacing value -gapSpacing value -maxWidth value -maxLength value -windowSize x y -windowStep x_step y_step -minDensity value -maxDensity value |
| 7 | setOptMode -opt_leakage_to_dynamic_ratio | Sets the ratio of leakage to dynamic power optimization effort. Setting to 1.0 focuses optimization entirely on leakage reduction | setOptMode -opt_power_effort {minimal | maximum} -opt_leakage_to_dynamic_ratio 0.8 |
| 8 | setMetalFill -activeSpacing | Sets the active area spacing rule for metal fill insertion. Controls the minimum distance between metal fill and active device areas | setMetalFill -activeSpacing value -gapSpacing value -maxWidth value -maxLength value -windowSize x y -windowStep x_step y_step -minDensity value -maxDensity value |
| 9 | setOptMode -opt_power_effort | Sets the power optimization effort level during optDesign. Controls the degree of power-driven timing optimization and leakage reclaim steps | setOptMode -opt_power_effort maximum -opt_leakage_to_dynamic_ratio 0.0 |
| 10 | setExtractRCMode -capFilterMode | Controls the capacitance filter mode for RC extraction. Setting to relAndCoup enables both relative and coupling capacitance filtering, ensuring extraction filters correlate to signoff extraction values | setExtractRCMode -capFilterMode relAndCoup |
| 11 | setOptMode -opt_leakage_to_dynamic_ratio | Sets the ratio of leakage to dynamic power optimization. Value of 1.0 prioritizes leakage; 0.0 prioritizes dynamic power | setOptMode -opt_power_effort maximum -opt_leakage_to_dynamic_ratio 0.0 |
| 12 | setOptMode -opt_allow_only_cell_swapping | Restricts post-Route optimization to LEF-safe cell swapping only, without any other physical transformations. Useful for congested designs where ECO routing detours have caused timing violations on final paths | setOptMode -opt_allow_only_cell_swapping true |
| 13 | set_power_analysis_mode -leakage_power_view | Sets the analysis view to use for leakage power optimization. Optimal view uses higher temperature corners (85/125°C) and typical libraries | set_power_analysis_mode -leakage_power_view leakage_view_name -dynamic_power_view dynamic_view_name |
| 14 | setNanoRouteMode -route_with_si_driven | Enables signal integrity-driven routing. Automatically enabled when running routeDesign for SI prevention | setNanoRouteMode -route_with_si_driven true |
| 15 | set_power_analysis_mode -dynamic_power_view | Sets the analysis view to use for dynamic power optimization | set_power_analysis_mode -leakage_power_view leakage_view_name -dynamic_power_view dynamic_view_name |
| 16 | setNanoRouteMode -route_with_timing_driven | Enables timing-driven routing. Automatically enabled when running routeDesign for SI prevention | setNanoRouteMode -route_with_timing_driven true |
| 17 | setOptMode -opt_power_effort | Sets the power optimization effort level. Impacts power-driven timing optimization, calls to leakage reclaim, and steps within preCTS optimization | setOptMode -opt_power_effort maximum -opt_leakage_to_dynamic_ratio 0.8 |
| 18 | setAnalysisMode -cppr | Enables Clock Path Pessimism Removal (CPPR). Setting to both enables CPPR for both setup and hold analysis, required for SI analysis in OCV mode | setAnalysisMode -analysisType onChipVariation -cppr both |
| 19 | setOptMode -opt_leakage_to_dynamic_ratio | Controls the ratio of leakage to dynamic power optimization. A value of 1.0 focuses on leakage; 0.0 focuses on dynamic power optimization | setOptMode -opt_power_effort maximum -opt_leakage_to_dynamic_ratio 0.0 |
| 20 | setAnalysisMode -analysisType | Sets the timing analysis type. onChipVariation mode enables OCV with simultaneous clock pushout/pullin for SI analysis | setAnalysisMode -analysisType onChipVariation -cppr both |
| 21 | setDesignMode -process | Sets the process technology node; automatically changes process-dependent default settings (e.g. RC extraction coupling capacitance thresholds) across all applications | setDesignMode -process 28 -flowEffort ultra |
| 22 | setDesignMode -flowEffort | Forces all super commands (place_opt_design, optDesign, routeDesign) to use extreme-effort settings for best timing/yield at the cost of runtime | setDesignMode -flowEffort ultra |
| 23 | setDesignMode -flowEffort | Forces all super commands (place_opt_design, optDesign, routeDesign, etc.) to use extreme-effort settings for best timing/yield at increased CPU runtime | setDesignMode -process 28 -flowEffort ultra |
| 24 | setNanoRouteMode -route_detail _use_multi_cut_via_effort | Sets the effort level for double-cut (multi-cut) via insertion during routing | setNanoRouteMode -route_detail_use_multi_cut_via_effort {minimal | medium | maximum} |
| 25 | setExtractRCMode -engine | Controls which RC extraction engine is used by extractRC. Use preRoute before detail routing and postRoute after NanoRoute detail routing. preRoute uses fast density measurements (no coupling); postRoute uses detailed distance measurements (coupling reported) | setExtractRCMode -engine postRoute |
| 26 | setNanoRouteMode -route_detail _post_route_spread_wire | Enables postroute wire spreading to significantly reduce signal integrity (SI) impact by spreading wires after routing | setNanoRouteMode -route_detail_post_route_spread_wire true |
| 27 | setExtractRCMode -effortLevel | Controls which post-route extractor is used, balancing performance vs accuracy. low=native detailed engine; medium=TQuantus (default for 65nm and below with Quantus techfiles, no extra license); high=IQuantus (superior accuracy, requires Quantus license); signoff=Standalone Quantus (highest accuracy, requires Quantus license) | setExtractRCMode -engine postRoute -effortLevel maximum |
| 28 | setNanoRouteMode -route_fix_clock_nets | Fixes clock nets during routing to prevent ECO changes; routeDesign sets this to false to allow ECO routing of clock nets after postCTS | setNanoRouteMode -route_fix_clock_nets true |
| 29 | setPlaceMode -place_design_floorplan_mode | Runs placement in prototyping mode for faster turnaround when true; must be set to false to produce legal placement when converging on a final floorplan | setPlaceMode -place_design_floorplan_mode true |
| 30 | setNanoRouteMode -route_with_timing_driven | Enables timing-driven routing using the Common Timing Engine (CTE); automatically set to true when timing information is loaded | setNanoRouteMode -route_with_timing_driven true |
| 31 | setPlaceMode -place_global_cong_effort | Increases numerical iterations and makes instance bloating more aggressive for congestion relief during global placement. Also automatically enables the congRepair command | setPlaceMode -place_global_cong_effort maximum |
| 32 | setOptMode -opt_hold_allow_overlap | Controls whether hold fixing is allowed to create cell overlaps during optimization. When set to true, hold optimization allows initial cell insertion to overlap cells, then refinePlace legalizes the placement. This provides optimization more opportunity to fix violations. Default (auto) allows overlaps during post-CTS but not post-Route optimization | setOptMode -opt_hold_allow_overlap true |
| 33 | setOptMode -opt_skew | Enables or disables useful skew optimization across all design flow steps (preCTS to postRoute). Setting to false disables useful skew in all flow steps | setOptMode -opt_skew true |
| 34 | setOptMode -opt_hold_ignore_path_groups | Excludes specified path groups from hold fixing during optimization | setOptMode -opt_hold_ignore_path_groups {groupA groupB...} |
| 35 | setOptMode -opt_setup_target_slack | Sets the target slack for setup timing optimization during pre-CTS or post-CTS optimization. Optimization focuses on paths that violate this target | setOptMode -opt_setup_target_slack -0.2 |
| 36 | setOptMode -opt_hold_allow_set up_tns_degradation | Controls whether hold fixing is allowed to degrade setup TNS (Total Negative Slack). By default, hold fixing can degrade setup TNS but not Setup WNS | setOptMode -opt_hold_allow_setup_tns_degradation true | true |
| 37 | setOptMode -opt_drv_margin | Sets the DRV (Design Rule Violation) margin for DRV fixing during optimization. Used to control how aggressively DRV violations are fixed | setOptMode -opt_setup_target_slack slack -opt_drv_margin value |
| 38 | setOptMode -opt_hold_target_slack | Sets the target hold slack for hold timing optimization. A negative value allows hold fixing to focus on paths with large violations first, leaving smaller violations to be fixed in later stages | setOptMode -opt_hold_target_slack -0.2 |
ChipBuddy
Innovus App Options
← Home
Comments
Leave a Reply