What Is an Engineering Change Order?

ECO types, unconstrained and metal-only flows, signoff-driven ECO, spare cells, timing fixes and verification

Imagine you have spent three months bringing a large block from raw RTL all the way to a clean, signed-off layout. Timing closes, the design-rule checks pass, the power grid is solid, and the database is frozen and archived. Then, on a quiet Tuesday afternoon, a verification engineer walks over and says: "We found a corner case in the reset logic. We need to swap one gate." Your first instinct might be panic. Do you really have to throw away three months of work and start over? The answer, almost always, is no. What you reach for instead is an Engineering Change Order, or ECO. Understanding ECOs is one of the clearest dividing lines between a junior physical-design engineer and a seasoned one. Anyone can run a flow from scratch when nothing has converged yet. The art lies in changing a finished design surgically, leaving everything that already works untouched. This chapter builds the mental model you will carry through the rest of the book.

A Working Definition

An engineering change order is a small, incremental modification applied to a design that is already complete or nearly complete. The keyword is incremental. You are not rebuilding; you are editing. The design has already been through the heavy lifting of synthesis, placement, clock-tree

construction, and routing. An ECO accepts that converged result as its starting point and makes the smallest possible set of changes to satisfy some new requirement. Think of it like editing a published book. If the publisher finds a single typo on page 412, they do not re-typeset the entire volume. They fix that one character, regenerate the affected page, and reprint. Everything else stays exactly as it was. An ECO is the silicon-design equivalent of that targeted correction.

The contrast that defines the value of an ECO is this:

When you re-run a full flow, every tool makes fresh decisions. Placement legalization shuffles cells, the router picks new tracks, and the clock tree may be rebuilt differently. The result is a design that is functionally equivalent to the old one but physically different everywhere. That difference is the enemy. It means every timing path, every signal-integrity check, and every design-rule region must be reverified from scratch. An ECO avoids that by preserving the converged state and disturbing only the region that genuinely needs to change.

Why ECOs Exist

ECOs are not a workaround or a sign that something went wrong. They are a planned, essential part of how complex chips reach tape-out on schedule. Several distinct pressures create the need for them.

Functional bug fixes. Late in the project, simulation or formal verification uncovers a logical error: a missing inversion, an incorrect mux select, a reset that does not propagate. The RTL fix might touch only a few gates, but the layout is already complete. An ECO patches the netlist and the layout to reflect the corrected logic. Timing fixes. Static timing analysis at signoff conditions, with final extracted parasitics and all corners, often reveals paths that miss their targets. Setup violations need faster cells or buffering; hold violations need added delay. These fixes are local by nature, which makes them ideal ECO candidates. Signal-integrity and noise fixes. Crosstalk-induced delay or glitches can push a path into violation or threaten functional robustness. The remedy, such as spacing nets apart, inserting shielding, or downsizing an aggressor, is a targeted layout edit. Design-rule cleanup. A final manufacturing-rule check may flag a small number of geometric violations. These get repaired without disturbing the rest of the layout. Late specification changes. Sometimes the requirement itself changes after implementation is done. A register default needs a different value, a test mode must be added, or an interface tweak arrives from the system architects. Rather than restart, the team absorbs the change through an ECO. In every one of these cases, the alternative, a full synthesis-place-route re-run, would be slower, riskier, and would destroy hard-won convergence. The ECO is what lets the team respond to late reality without sacrificing the schedule.

The Core Value: Preserve Convergence, Touch as Little as Possible

If you remember only one sentence from this chapter, make it this: the goal of an ECO is to preserve the converged design and change as little as humanly possible. Every cell you move, every net you reroute, and every buffer you insert is a potential source of new violations. A path that was comfortably closed can be pushed into failure simply because a neighboring net moved and changed the coupling capacitance. Discipline about minimizing disturbance is what separates a clean ECO from a chain of follow-on ECOs chasing problems you created yourself. This principle drives nearly every decision in ECO methodology. It is why we prefer to reuse existing cells over adding new ones, why we lock down already-routed nets, and why we run incremental placement and routing rather than global versions. The tools support modes that explicitly honor the existing solution and confine their work to a small bounding region around the change.

Categories at a Glance

ECOs are classified along a few independent axes. A single ECO sits at one point on each axis simultaneously, so it helps to learn them as separate dimensions.

Functional versus timing/SI. A functional ECO changes what the circuit does. The logic of the netlist is different afterward, so it must pass logical equivalence checking against the new reference RTL. A timing or SI ECO, by contrast, does not change the logic at all. Resizing a buffer or adding a delay element leaves the boolean function untouched; you are only changing the electrical behavior. This distinction matters enormously for verification: timing-only ECOs are far cheaper to sign off because the function is provably unchanged. Pre-tape-out versus post-tape-out. Before the design is sent to the foundry, you have full freedom. You can move cells, add new instances anywhere, and reroute on any layer. After tape-out, or for a metal-revision spin of already-fabricated silicon, your freedom collapses. The base layers, the transistors themselves, are already committed to manufactured wafers. You can only change the upper metal masks. This constraint gives rise to the most disciplined and economically important category of all. All-layer versus metal-only. An all-layer ECO may place brand-new physical cells and route them using any layer. A metal-only ECO is forbidden from adding new transistors. It must build any required new logic out of cells that are already physically present on the die but currently unused. The motivation is cost: re-spinning only the metal masks is dramatically cheaper than re-spinning the full mask set, because the expensive base layers stay fixed. Metal-only ECOs are the reason chips carry a scattering of pre-placed unused gates, which brings us to vocabulary.

Where ECOs Sit in the Lifecycle

ECOs are a late-stage activity. They presuppose that a full implementation pass has already happened. The typical position in the flow looks like this:

1. 1. Synthesis turns RTL into a gate-level netlist.
2. 2. Floorplanning, placement, clock-tree synthesis, and routing build the physical layout.
3. 3. Signoff checks run: static timing analysis, signal-integrity analysis, power analysis, and physical

verification.

1. 4. A problem or change request surfaces.
2. 5. An ECO loop generates a small set of changes, applies them incrementally, and re-verifies only

the affected scope.

1. 6. Steps 4 and 5 may repeat several times until the design is truly clean.

The defining feature of step 5 is that it does not send you back to step 1. The converged database from step 2 is the input, and incremental engines do the work. A chip near tape-out may go through dozens of ECO iterations, each one nudging the design closer to a fully clean state without ever restarting.

Key Vocabulary

A few terms appear constantly in ECO work, and getting comfortable with them now will make later chapters smoother. Spare cells. These are extra logic gates, things like inverters, NANDs, flip-flops, and tie cells, that are deliberately scattered across the floorplan during the original implementation, placed and powered but with their inputs and outputs left unused. They are an insurance policy. When a metal-only ECO needs new logic after tape-out, it cannot add transistors, so it builds the fix by rewiring these dormant spare cells. A well-distributed spare-cell population is what makes post-silicon metal fixes possible. Metal-only change. Any modification that touches only the routing (metal and via) layers, leaving the base transistor layers untouched. This is the cheapest class of revision because the costly base masks are reused. Incremental placement and routing. Specialized tool modes that operate on an existing converged layout, confining new work to a small region and preserving everything outside it. Instead of placing all cells, incremental placement legalizes only the few new or moved cells. Instead of ripping up the whole design, incremental routing connects only the new nets while honoring existing wires. Change record. The auditable description of exactly what an ECO did: which cells were added, removed, or resized, which nets were rerouted, and why. The change record is what lets a team review, reproduce, and verify an ECO, and it is essential for tracking which spare cells have been consumed across multiple revisions. A typical ECO directive file is a short, human-readable list of operations. Using generic command names, a functional fix might look like this:

# Functional ECO: correct a missing inversion on the enable path
eco_begin -name fix_enable_polarity
disconnect_pin   -inst u_ctrl/and_gate -pin A
create_instance  -ref INV_X1 -name u_ctrl/eco_inv0
connect_net      -net  ctrl_enable_n   -pin u_ctrl/eco_inv0/A
connect_net      -net  ctrl_enable_buf -pin u_ctrl/eco_inv0/Y
connect_pin      -inst u_ctrl/and_gate -pin A -net ctrl_enable_buf
eco_end

A metal-only timing fix, by contrast, reuses existing spare cells rather than creating new instances:

# Metal-only ECO: fix a hold violation using a pre-placed spare delay cell
eco_begin -name fix_hold_path -mode metal_only
map_to_spare_cell -logical eco_delay0 -physical spare/dly_buf_47
insert_buffer     -net data_to_reg -cell eco_delay0
report_spare_usage
eco_end

Notice that the metal-only example never calls create_instance . It maps a needed function onto a spare cell that already physically exists, which is the whole point of the metal-only discipline.

Interview Q&A

flow? An ECO is a small, incremental change applied to an already-converged design, and you use it because re-running the full flow would discard all the closed timing, signal-integrity, and physicalverification results and force you to re-verify a design that is now physically different everywhere, whereas an ECO preserves convergence and disturbs only a tiny region.

standpoint? A functional ECO changes the logic, so it must pass logical equivalence checking against the updated reference design to prove the new function is correct. A timing or SI ECO does not change the boolean function at all, so equivalence is preserved by construction, and you only need to re-confirm timing and electrical behavior. This makes timing-only ECOs significantly cheaper to sign off.

Spare cells are pre-placed, powered, but unused gates distributed across the die so that a metal-only ECO has logic to work with. The constraint is that after tape-out you cannot add transistors, only change metal masks. Since metal-only fixes cannot create new cells, any new logic must be built by rewiring spare cells, so an adequate spare-cell population is the prerequisite for cheap post-silicon fixes.

principle?

In practice it means reusing existing cells where possible, locking already-routed nets, and running placement and routing in incremental modes that confine work to a small bounding region. It is the guiding principle because every cell moved or net rerouted can perturb a previously closed path, for example by changing coupling capacitance, so minimizing disturbance directly minimizes the risk of creating new violations and triggering further ECO iterations.

Key Takeaways

• An ECO is a small, incremental edit to an already complete or nearly complete design; it edits rather than rebuilds.
• ECOs exist to fix functional bugs, timing, signal-integrity, and design-rule issues, or to absorb late spec changes, all without re-running full synthesis, placement, and routing.
• The core value is preserving the converged result and touching as little as possible, because every change is a chance to break something that already worked.
• ECOs are classified on three independent axes: functional versus timing/SI, pre-tape-out versus post-tape-out, and all-layer versus metal-only.
• Metal-only ECOs reuse pre-placed spare cells because the base transistor layers are already committed; this makes post-silicon revisions far cheaper than a full mask re-spin.
• ECOs live at the tail end of the lifecycle, after a full implementation and signoff pass, and feed an iterative loop that uses incremental placement and routing.
• Core vocabulary to internalize: spare cells, metal-only change, incremental placement and routing, and the change record that documents every edit.