ECO Optimization & Sign-off Closure
Closing the Last Gap: ECO-Driven Optimization
By the time a block is routed and analyzed at signoff quality, the remaining violations are usually few but stubborn. Re-running full optimization would disturb everything that already works. Instead, closure is done with engineering-change-order (ECO) optimization: small, surgical edits aimed only at the residual problems, applied incrementally and re-verified. The defining idea is minimal disturbance — touch as little as possible, preserve everything already closed, and confirm after each change. The later the stage, the smaller the allowed edit.

| Stage of closure | Edit size | Typical action |
|---|---|---|
| Early opt | large | restructure, resize freely |
| Late opt | medium | sizing, buffering |
| ECO closure | minimal | spare/in-place swaps, single buffers |
Signoff-Timing-Driven ECO
In-tool timing and signoff-grade timing rarely agree perfectly, because signoff uses full parasitics, more corners, and stricter analysis. Closing on the tool's own numbers can leave you still failing at signoff — an endless ping-pong. Signoff-timing-driven ECO breaks the loop: you derive the fix list from the signoff analysis itself, apply those ECOs in the implementation tool, then re-extract and re-run signoff. Because the changes target the authoritative numbers, the design actually converges.
# Read a signoff-derived fix list and apply it in-tool
# illustrative — generic, not tool-specific
read_eco_changes signoff_fixes.eco
optimize_timing -mode eco -respect_signoff true
# Re-extract and re-check at signoff quality
# illustrative — generic, not tool-specific
extract_parasitics -incremental
report_timing -delay setup -delay hold
For large or hierarchical designs, a top-down block ECO flow driven by signoff timing pushes the chip-level signoff picture down to each block so block owners fix against the same authoritative context, then results reassemble at the top.

Metal-Only ECO and the One-Pass Equivalence Check
After tape-out preparation, base layers may be frozen, so only metal and via masks can change. Metal-only ECO realizes fixes using pre-placed spare cells and rewiring, with no new base geometry — far cheaper to respin. Optimization in this mode is constrained to what spares and routing allow. Every netlist-changing ECO must remain logically equivalent to the golden design (unless the ECO is itself a deliberate functional change). A one-pass logical equivalence check (LEC) confirms this efficiently: it compares the modified netlist against the reference in a single reconciliation, using the change/mapping records so it knows what was intentionally altered. Running LEC after each ECO batch keeps function provably intact.
# Constrain ECO to metal-only using spare cells
# illustrative — generic, not tool-specific
optimize_timing -mode eco -metal_only true -use_spares true
# Confirm logical equivalence to the golden netlist
# illustrative — generic, not tool-specific
check_equivalence -reference golden.v -implementation eco.v -one_pass true
A frequent late fix is rebuffering an integrated-clock-gate (ICG) enable: the enable path into a clock gate is timing-sensitive, and inserting or resizing buffers on it (within ECO limits) recovers its slack without disturbing the clock tree itself.
| ECO type | Layers changed | Enabler | Use |
|---|---|---|---|
| All-layer ECO | base + metal | new cells allowed | pre-tape-out |
| Metal-only ECO | metal/via only | pre-placed spares | post-tape-out respin |
| In-place swap | none (same footprint) | footprint-compatible cells | any late fix |
The Optimization Sign-Off Checklist
Before declaring optimization complete, confirm the design across every objective, in every active mode and corner:
- Setup: no negative WNS; TNS within budget across all corners/modes (signoff-confirmed).
- Hold: clean across all corners; hold fixes did not erode setup.
- Design-rule violations: max-transition and max-capacitance clean everywhere.
- Signal integrity: crosstalk delta-delay, glitch, and SI slew within limits after real extraction.
- Power: dynamic and leakage within budget; Vt mix healthy; no power-pass-induced timing breakage.
- Equivalence: LEC clean after every netlist-changing ECO.
- Consistency: in-tool and signoff timing agree; multi-corner/multi-mode all satisfied.
- Minimal disturbance: ECO edits localized; previously closed timing preserved.

| Symptom | Likely cause | Lever |
|---|---|---|
| Passes in-tool, fails signoff | optimistic in-tool analysis | signoff-driven ECO |
| Hold fixed but setup broke | over-aggressive hold buffering | rebalance / downsize |
| Power met but timing slipped | greedy power pass | setup-recovery pass |
| SI delta-delay violations | crosstalk after routing | shield / space / upsize victim |
| Endless re-optimization | open-ended targets | target-based + target file |
Command Quick Reference
Standard, portable commands (work across compliant tools):
# standard (SDC) — constraints the whole flow relies on
create_clock -period 10 [get_ports clk]
set_max_transition 0.30 [current_design]
set_false_path -from [get_clocks clkA] -to [get_clocks clkB]
set_multicycle_path 2 -setup -to [get_pins reg_b/D]
Illustrative, vendor-neutral commands used in this book (convey the step; not real tool syntax):
# illustrative — generic, not tool-specific
optimize_timing -mode {pre_cts | post_cts | post_route | eco}
optimize_power -mode {leakage | dynamic | total}
merge_multibit -max_bits 4 ; split_multibit -instances {...}
generate_target_file -from_violations -out close.tgt
read_eco_changes signoff_fixes.eco ; check_equivalence -one_pass true
Interview Q&A
Because a full re-run disturbs everything already closed and risks new violations. ECO optimization makes minimal, surgical edits aimed only at the residual problems and re-verifies after each, preserving the converged result.
signoff timing. Deriving the fix list from signoff analysis and applying it in-tool, then re-extracting and re-running signoff, makes the design converge on the authoritative numbers instead of ping-ponging.
realized using pre-placed spare cells and rewiring with no new base-layer geometry. Respinning only metal masks is far cheaper and faster than a full mask set, which is why spares are stocked before tape-out.
equivalent to the golden design. A one-pass LEC, using the change/mapping records, confirms function is intact (or that only intended changes were made) efficiently after each batch.
trades positive slack for savings (e.g., higher-Vt swaps) and can erode or break timing. A focused setup-recovery pass reverses only the costliest moves on now-critical paths, restoring closure while keeping most of the power savings.
Key Takeaways
- Final closure uses ECO optimization: minimal, surgical, re-verified edits — the later the stage, the smaller the allowed change.
- Signoff-timing-driven ECO fixes against the authoritative analysis so in-tool and signoff agree; a top-down block ECO flow scales this hierarchically.
- Metal-only ECO uses pre-placed spares for cheap post-tape-out respins; always follow netlist edits with a one-pass equivalence check.
- Sign off only when setup, hold, DRVs, SI, power, equivalence, and MCMM consistency all pass with minimal disturbance.
- Remember the command distinction: SDC constraints are real and portable; the optimization verbs in this book are illustrative and not tool-specific.
ChipBuddy
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