Power Optimization: Leakage, Dynamic & Total

Pre-CTS, post-CTS, post-route optimization, useful skew, SI fixes, leakage reduction and ECO closure

Power as an Optimization Objective

For most of this handbook, timing has been the headline goal. In a modern design, power sits right beside it as a co-equal target, and the optimizer is expected to drive both at once. A chip that meets frequency but blows its power budget is just as unshippable as one that is too slow. The difficulty is that the cheapest way to fix timing — bigger, faster cells — is also the most power-hungry, so timing and power pull in opposite directions and the optimizer has to find the balance. Power has two distinct components, and they respond to completely different levers:

• Dynamic (switching) power is burned every time a node toggles. It scales with switching activity, the capacitance being driven, and the square of the supply voltage. You reduce it by making nodes toggle less often or by driving less capacitance.
• Leakage (static) power is burned continuously, whether or not anything switches, because real transistors conduct a small current even when "off." It grew from a rounding error at older nodes into a dominant share at advanced nodes, and it is exquisitely sensitive to threshold voltage (Vt).

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Short-circuit / slew, drive vs load clean transitions, right-sizing The golden rule that organizes the whole chapter: recover timing slack first, then spend it on power. Every power move that helps (a higher-Vt cell, a smaller gate) costs a little speed. So the optimizer first creates margin where it can, then trades that margin for power savings only on paths that can afford it.

Leakage Power Optimization

Leakage optimization is the highest-leverage power technique at advanced nodes, and the cleanest because it can often be done without moving anything.

Multi-Vt swapping

Standard-cell libraries ship the same logical cell in several threshold-voltage flavors — typically high-Vt (HVT, lowest leakage, slowest), standard-Vt (SVT), and low-Vt (LVT, fastest, leakiest). Crucially, these variants are usually footprint-compatible: a cell can be swapped for another Vt flavor of the same size without disturbing placement or routing, because it occupies the same area and pin locations. The optimizer exploits this directly. It ranks cells by how much positive slack their path has and how much leakage they contribute, then swaps the leakiest cells on the most slack-rich paths to a higher

Vt. A cell sitting on a path with 300 ps of spare slack can almost always move to HVT for a large leakage win and a small, affordable delay increase.

# Leakage optimization on a footprint-preserving basis
# illustrative — generic, not tool-specific
optimize_power -mode leakage -preserve_footprint true
# Restrict which Vt flavors the optimizer may use
# illustrative — generic, not tool-specific
set_vt_swap_candidates {HVT SVT LVT}
# Report the resulting Vt mix and leakage
# illustrative — generic, not tool-specific
report_power -leakage -by_vt

The key discipline is to keep critical paths on fast cells and push everything else up. A healthy design ends with the large majority of cells at high Vt and only a thin slice of LVT confined to the genuinely critical paths.

Dynamic Power Optimization

Dynamic power needs different moves because it is about activity and capacitance, not leakage current.

• Clock gating is the single biggest dynamic lever: shut off the clock to registers that are not doing useful work in a given cycle, so they stop toggling. The optimizer can insert or improve gating and merge gating logic.
• Activity-aware restructuring: high-toggle nets are expensive, so restructuring logic to keep frequently switching signals on smaller capacitance — or moving them closer to their sinks — saves dynamic power.
• Downsizing and pin swapping: a cell driving a light load can be downsized to present less input capacitance; swapping a high-activity signal to a lower-capacitance input pin of a gate reduces the switched cap. # Dynamic power optimization driven by switching activity # illustrative — generic, not tool-specific read_activity my_design.saif optimize_power -mode dynamic -activity_driven true Activity data (from simulation, in a switching-activity file) makes these decisions far better than guessing, because the optimizer learns which nets actually toggle often versus which are nominally wide but quiet. Dynamic technique Mechanism Caution Clock gating stops idle-register toggling enable timing, gating overhead

Treating leakage and dynamic separately leaves savings on the table because the two interact — a downsizing move helps both, while a Vt swap helps only leakage. Total-power optimization minimizes the combined figure jointly, respecting timing constraints across all active modes. Because power varies by operating mode (a sleep mode and a peak-performance mode burn very differently), the optimizer can do per-mode, power-driven optimization so that each mode's dominant power component is attacked appropriately.

A large power optimization pass — especially aggressive Vt up-swapping — deliberately consumes positive slack. If pushed too far it can turn comfortable paths into marginal ones or even create new violations. The standard remedy is a setup-recovery pass afterward: the optimizer re-examines timing and selectively reverses the few power moves that cost the most slack (swapping a handful of cells back to a faster Vt, or upsizing a critical stage), restoring closure while keeping the vast majority of the power savings.

# Recover setup eroded by an aggressive power pass
# illustrative — generic, not tool-specific
optimize_timing -mode setup_recovery -from last_power_pass
report_timing -delay setup ; report_power

The ordering matters: power-then-recover is far more effective than trying to hold timing perfectly during the power pass, because letting the power pass be greedy and then clawing back only the critical exceptions reaches a better overall point.

Interview Q&A

swaps are footprint-preserving — they change leakage and a little delay without disturbing placement or routing — so they are low-risk and reversible. You get most of the leakage win without churning the design, and you keep restructuring (which has a larger blast radius) for cases swaps cannot solve.

the clock network and the registers it drives toggle every cycle and dominate dynamic power; switching off idle registers removes that activity entirely rather than just shaving capacitance.

trades positive slack for savings and can erode or break timing. A recovery pass reverses only the few highest-cost power moves on now-critical paths, restoring closure while preserving the bulk of the savings — a better endpoint than constraining the power pass to never touch slack.

nodes actually switch. Without activity data the optimizer treats all nets as equally important; with a switching-activity file it focuses effort on the genuinely high-toggle nets, where reducing capacitance or gating yields real savings.

Key Takeaways

• Power has two components with different levers: dynamic (activity × cap × V², attacked by clock gating, restructuring, downsizing) and leakage (Vt-driven, attacked by multi-Vt swapping).
• Recover slack first, then spend it on power — every power move costs a little speed.
• Multi-Vt swapping is the workhorse for leakage because it is footprint-preserving and low-risk; aim for mostly HVT with LVT confined to critical paths.
• Total-power optimization minimizes leakage and dynamic jointly and per-mode; follow a large power pass with a setup-recovery pass.
• Real switching-activity data makes dynamic optimization dramatically more effective.