27 Static Timing Analysis

STA fundamentals — cell delay, interconnect, setup/hold, MCMM, OCV, noise, IR-drop and sign-off

How to Use This Bank

This is a fast question bank. It covers the basics that an STA interview almost always asks. Each answer is short. You should be able to say it out loud in about 25 seconds. Practice the reasoning, not just the words. The next chapter pushes into harder cases.

Concept Fundamentals

What is static timing analysis in one sentence? It checks that a design meets its timing. It does

this without test inputs. It walks arrival times through the timing graph. Then it tests every path against setup and hold.

Why "static" rather than simulation? Simulation only tests the paths your inputs reach. So it is

slow and misses paths. STA checks all paths fast, with no inputs. The trade-off: it checks timing only, not function.

What does STA not do? It does not check logic function. It cannot time real async crossings well.

It is only as good as your constraints, libraries, and parasitics.

Define slack. Slack is how much a check passes by. For setup it is required time minus arrival

time. For hold it is arrival minus required. Positive means it passes. Negative means it fails.

What are arrival time and required time? Arrival time is when a signal really reaches a node. It

moves forward from startpoints. Required time is the latest (setup) or earliest (hold) the signal may arrive. It moves backward from endpoints.

What is the critical path? It is the path with the worst slack. For setup, it caps the clock speed.

For hold, it is the most at risk.

Name the four path groups. Input-to-register, register-to-register, register-to-output, and input-to-

output. The last one is pure combinational. Each one is constrained in its own way.

What is a startpoint and an endpoint? A startpoint is a register clock pin or a primary input. An

endpoint is a register D pin or a primary output.

Delay and Slew

What two variables set a cell's delay in a lookup model? Input slew and output load. The tool

reads delay and output slew from 2-D tables. It interpolates between table points.

What is slew and why does it matter? Slew is the rise or fall time of a signal. Slow slew adds

delay. It also makes timing more sensitive to variation. It worsens noise and power too. So STA sets a max-transition rule.

Why are current-source models more accurate than table models? They model the output

as a current source. It drives the real RC net. This captures waveform shape and resistive effects. A single delay table cannot do this at small nodes.

What is effective capacitance? A resistive net shields the driver from the far load. So the driver

"sees" less than the total wire cap. Delay math uses this smaller value, not the full lump.

What is unateness? It is how an output edge follows an input edge. Positive-unate: input rise

gives output rise. Negative-unate: input rise gives output fall. Non-unate: both, like an XOR. It sets which edges form timing arcs.

How is interconnect delay modeled? From simple to accurate: lumped cap, then lumped RC,

then distributed RC trees. Elmore delay gives the idea. Downstream resistance times cap builds up along the tree.

Setup and Hold

State the setup check. Data is launched at the launch edge. It must reach the capture D pin

before the capture edge minus setup time. You also adjust for skew and uncertainty. This sets the top clock speed.

State the hold check. Data must not reach D too soon after the same capture edge. It must stay

stable for the hold time. This stops a fast new value from racing through. It does not depend on the clock period.

Why does setup scale with frequency but hold does not? Setup looks at the next edge, one

period away. A shorter period makes it tighter. Hold looks at the same edge. The period cancels out. So hold depends only on skew and min delay.

How does positive clock skew affect setup and hold? Positive skew means capture is later

than launch. This helps setup, since data has more time. It hurts hold, since data can race through. Negative skew does the opposite.

A path passes setup but fails hold — is increasing the clock period a fix? No. Hold does not

depend on the period. A longer period does nothing. Fix hold with delay buffers, less skew, or slower min-delay cells.

What is recovery and removal timing? They are setup and hold checks for async set or reset

release. Recovery is like setup. Removal is like hold. Together they make the flop exit reset cleanly.

Clocks and Constraints

What does create_clock define? It sets the clock period, waveform, and source. Every

synchronous check is measured against it.

Source latency vs network latency? Source latency is the delay from the true origin to the

clock-definition point. Network latency is the delay through the on-chip clock tree to the register. Added together they give total latency.

Ideal vs propagated clock? An ideal clock assumes zero tree delay. This is used before CTS,

with uncertainty for skew and jitter. A propagated clock uses real tree delays after CTS. It gives true skew.

What is clock uncertainty and what does it bundle? It is a margin added to checks. It bundles

skew, jitter, and extra guardband before the real tree exists. It tightens both setup and hold. Real skew mostly replaces it after CTS.

What is jitter? It is cycle-to-cycle change in where the clock edge lands. It comes from the

source or PLL. It eats margin, mostly setup. It is part of uncertainty.

Why declare generated clocks? So the tool knows the exact edge link to the master clock. Get

it wrong and the tool picks wrong capture edges. The slack then makes no sense.

What do set_input_delay and set_output_delay do? They model off-chip timing at the ports

against a clock. They say how much of the period is used outside the chip. Max values drive setup. Min values drive hold.

What is a virtual clock? It is a clock with no physical pin. You use it to tie I/O delays to an

external clock that is not a real port here.

Why model the port environment (driving cell, external load)? So input slews and output

loads at the edge are realistic. Without it, boundary path delays are wrong.

What happens to unconstrained paths? They are not checked. So real violations can hide. A

good constraint review flags any uncovered endpoints.

Exceptions

What is a false path? It is a real path that can never be active in function. An example is two

mutually exclusive modes. Declaring it drops false violations. The tool then does not over-design.

What is a multicycle path and its classic trap? It is a path given more than one cycle to settle.

The trap: a setup multicycle of N moves the capture edge out. But the default hold check lands on the wrong edge. You must add a matching hold multicycle, usually N−1, to pull it back.

set_max_delay/set_min_delay — when? Use them to bound a path's delay directly. This

ignores clock-derived limits. It is common for I/O or async datapaths.

What does set_case_analysis do? It fixes a pin to a constant. This prunes dead logic and picks

a mode. It speeds analysis and drops impossible paths.

Why is over-constraining dangerous? A too-broad exception can hide real violations. This

happens on paths that share its scope. Always declare the narrowest correct exception.

Variation and Corners

What is a PVT corner? It is a mix of Process, Voltage, and Temperature. It brackets the silicon

spread. Libraries are characterized for each corner.

Which corner is typically worst for setup vs hold? Setup is usually worst at slow process, low

voltage, hot. Hold is usually worst at fast process, high voltage, cold. Watch the temperature-inversion exception at low voltage.

What is temperature inversion? At low supply voltage, delay can drop as temperature rises.

This is the opposite of the usual trend. So "hot equals slow" breaks. You must check both temperature extremes.

What is timing derating? It is a multiplier on delays. It adds cheap margin for variation. A late

derate slows data for setup. An early derate speeds it for hold.

What is OCV? On-chip variation. It models that launch and capture paths on one die may differ

in speed. It applies opposite derates. It is simple but pessimistic.

What is CPPR/CRPR? Common-path pessimism removal. The shared clock trunk should not

get opposite derates. Removing that double count gives back large, false-looking slack.

What is MCMM? Multi-corner multi-mode. It analyzes many modes and corners at once. You

sign off on the worst across all active scenarios.

Quick-Fire Definitions

Interview Q&A Bank — Fundamentals

Term	One-line answer
WNS / TNS	worst / total negative slack across endpoints

Does adding clock period help hold? No — hold does not depend on the period. Q44. Which

is fixed by skew + min delay, setup or hold? Hold. Q45. Where does effective capacitance come from? The net shields the far cap from the driver. Q46. What removes shared-clock pessimism? CPPR. Q47. Up-shifter is needed when a signal goes from…? A lower-voltage domain to a higher one. Q48. What does a false path tell the tool? That the path is never active — do not check it. Q49.

What metric captures total design setup health? TNS, with WNS for the worst single path. Q50. Propagated clock is used when? After CTS, when real tree delays exist.

Key Takeaways

Be able to define and derive setup and hold. Explain why setup scales with frequency but hold does not.
Know the clock vocabulary cold: latency, uncertainty, skew, jitter, ideal vs propagated, generated clocks.
Explain constraints and exceptions clearly, including the multicycle hold trap and the danger of over-constraining.
Cover corners, derating, OCV, CPPR, and MCMM. Know which corner is worst for setup vs hold, and temperature inversion.
Practice answering in about 25 seconds with reasoning, not just definitions.

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