Multiple Supply Voltage & Voltage Areas

UPF/CPF power intent, isolation cells, level shifters, retention flops, power gating and MSV flows

Why One Voltage Is Never Enough

If you remember a single equation from your low-power studies, make it this one: dynamic switching power scales with the square of the supply voltage, P_dyn ≈ α · C · V² · f . The quadratic term is the lever. Drop the rail feeding a block from 0.90 V to 0.72 V and, all else equal, you cut its dynamic power to roughly 64% of the original — a 36% saving for a 20% voltage reduction. Nothing else in the designer's toolbox gives you that kind of leverage so cheaply. The catch is that lowering voltage also lowers transistor drive strength, so gates get slower. A path that closed timing at 0.90 V may violate at 0.72 V. This is the whole tension that Multiple Supply Voltage (MSV) design exists to resolve: match each block's supply voltage to the performance it actually needs, instead of running the entire die at the voltage demanded by its single most timing- critical corner. A modern SoC is rarely uniform in its performance appetite. A CPU cluster or a high-throughput accelerator may genuinely need the top rail to hit its frequency target. But a configuration register file, a low-bandwidth peripheral bridge, a sensor-data preprocessor, or an always-listening wake block typically have enormous timing slack. Forcing them to share the CPU's aggressive rail wastes power every cycle they switch. MSV lets you carve the design into regions, each on a rail sized to its job.

It helps to see MSV as one point on a spectrum of voltage-based techniques. Static voltage scaling assigns a fixed lower rail to a permanently slack block. Multi-voltage design generalizes that to several fixed rails across the die. Dynamic Voltage and Frequency Scaling (DVFS) goes further, sliding a block's rail up and down at run time as its workload changes. Adaptive Voltage Scaling closes the loop with on-die monitors that trim the rail to the silicon's actual speed. All of these rest on the same physical foundation — physically separated supply regions — and that foundation is the voltage area. Master voltage areas and you have the substrate on which every one of these schemes is built. The synthesis and signoff tools also need to characterize each block at the specific operating voltage it will see, which is why MSV multiplies the number of timing corners you must close: a block that can run at two voltages must meet timing at both.

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fill="#16324f" font-size="12.5" text-anchor="middle" font-weight="800">A chip
partitioned into power domains</text></svg><figcaption><span class="figlabel">Figure
4.1</span> SoC die divided into three colored regions — high-voltage CPU
cluster (0.90V), mid-voltage DSP (0.81V), low-voltage peripheral block
(0.72V) — each fed by its own power rail from the PMU</figcaption></figure>

The table below shows the core trade-off that drives every voltage-assignment decision.

voltage

Logical Power Domains vs. Physical Voltage Areas

Two terms get used loosely in conversation and conflated by junior engineers, so let's be precise — interviewers probe exactly this distinction. A power domain is a logical construct. It is a named grouping of design instances that share a common power-supply intent: the same primary supply, the same ground, the same shutdown behavior, the same retention strategy. You declare power domains in your power-intent file — the IEEE 1801 (UPF) or CPF description that travels with the design from synthesis through signoff. At this stage there is no geometry; a domain is just a set of logic plus rules about how it is powered. A voltage area (some flows call it a power region) is the physical realization of that intent. It is a fenced-off rectangle or rectilinear region of the floorplan into which the placer is constrained to put that domain's standard cells, and over which the appropriate power rails are routed. The voltage area is where the abstract "this logic runs at 0.72 V and can be shut down" becomes "these placement rows, in this part of the die, are wired to the VDD_LOW rail and the switch fabric that gates it." The relationship is usually one logical power domain maps to one physical voltage area, but the mapping is not forced to be that clean. A single domain can be split across two disjoint regions if the floorplan demands it, and tools allow it — though it complicates rail planning and isolation. What you must never do is let a domain's cells land outside any region designated for that domain. That is the single most common MSV bug, and we return to it under pitfalls. Why keep the two concepts separate at all? Because they are owned by different stages of the flow and serve different verification goals. The logical power domain is what lets functional and power- aware checks reason about correctness long before any geometry exists — at RTL you can already

ask "is every crossing isolated?" and "is retention specified for the right registers?" The voltage area is what lets the physical tools enforce that intent in silicon: it gives the placer a fence, gives the powerplanning engine a rail map, and gives the router a place to put boundary cells. A clean MSV methodology treats the power-intent file as the single source of truth and regards the voltage area as the mechanism that makes the physical implementation obey it. When the two disagree — a cell in the wrong region, a rail wired to the wrong net — you have an intent-versus-implementation mismatch, and catching those is exactly what power-aware verification exists to do.

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power domains; right column "Physical: voltage_area_core,
voltage_area_peri" rectangles on the floorplan; arrows showing PD maps
to VA</figcaption></figure>

Rules at the Borders of a Voltage Area

The interesting engineering — and most of the interview questions — live at the boundaries between voltage areas. A signal that leaves one region and enters another may be crossing a voltage boundary, a power-state boundary, or both. Each crossing imposes a structural requirement. Level shifting on voltage crossings. When a signal driven at one voltage feeds a gate powered at a different voltage, a plain wire is not enough. A high-to-low crossing can sometimes function but burns

excess power and leaves margin on the table; a low-to-high crossing frequently fails to switch the receiver fully, leaving the input transistor partially on and causing static current and unreliable logic levels. The fix is a level shifter — a special cell that translates one voltage swing to another. The rule of thumb: every signal that crosses a voltage boundary needs a level shifter, and that shifter must be physically located so it is itself reliably powered by the supplies it bridges. Level shifters that need both rails are often placed right at the border, sometimes in a dedicated row. Isolation when a region can power down. If a voltage area can be switched off while a neighbor stays on, the signals leaving the off region float to indeterminate values. Those floating nets can corrupt the live logic and cause crowbar current in receiving gates. Isolation cells clamp each crossing output to a known, safe value (clamp-to-0, clamp-to-1, or latch-last-value) during shutdown. Isolation cells must themselves sit on an always-on supply, because they have to work precisely when the source domain is dark. A crossing into a power-switchable region may therefore need both a level shifter and an isolation cell — sometimes combined in a single enable-level-shifter cell. Row, site, and rail planning inside the region. Within a voltage area, the placement rows must be built on the site/track grid of the library variant that operates at that region's voltage, and the power rails laid into those rows must connect to the region's supply, not the chip-wide default. If the region is switchable, the rails connect through the power-switch fabric (header or footer switches), and the switch-enable network plus an always-on backbone for retention and isolation control must be planned into the same rows. Getting the rail and rows wrong here is what produces unconnected power pins or shorts between rails at the boundary.

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svg><figcaption><span class="figlabel">Figure 4.3</span> Cross-section of a voltage-
area border — source region cell,
then a level shifter and isolation cell sitting in a border row on
always-on rail, then destination region cell; rails labeled VDD_LOW,
VDD_HIGH, VDD_AON</figcaption></figure>

Always-On Regions, Scalable Regions, and Nesting

Not every region behaves the same way over time. An always-on (AON) region holds logic that must never lose power: the power-management controller that decides who gets switched, the isolation and switch-enable drivers, retention control,

and any wake or reset logic. AON regions are typically modest in voltage and area but are nonnegotiable — if they go dark, nothing can wake the rest of the chip. A scalable (or switchable/variable) region is one whose supply changes over time. It may be gated off entirely to eliminate both dynamic and leakage power, or it may sit on a rail that the system slews between discrete voltage points depending on workload (the dynamic-voltage side of DVFS). Its borders therefore need the full complement of isolation and level-shifting machinery, and timing must be verified at every operating voltage the region can take, not just one. Nested voltage areas occur when one region physically sits inside another. A classic case: a small always-on retention island embedded within a larger switchable region, so that a handful of stateholding cells survive while the bulk of the surrounding logic is powered down. Nesting is powerful but raises the boundary-rule burden — the inner border now has its own crossing rules with respect to the outer region, and rail planning must thread the always-on supply down into the inner island without shorting the switchable rail around it. A useful mental model for the time dimension is the power state table: an enumeration of which regions are on, off, or at which voltage in each legal system mode (active, idle, deep-sleep, and so on). The crossing rules at a border are ultimately derived from this table — a level shifter is needed wherever two regions sit at different voltages in some legal state, and isolation is needed wherever one region is off while a neighbor it drives is on in some legal state. If a state combination is genuinely impossible (the table forbids it), you may legitimately drop the cell that would otherwise be required. This is why the power state table is not paperwork: it directly determines how many special cells your

borders carry, and therefore how much area and congestion the MSV scheme costs.

Floorplanning Considerations

The physical designer earns their keep deciding the shape, size, and placement of voltage areas. A few principles:

• Shape and size. Prefer compact, convex (ideally rectangular) regions. Long, thin, or heavily notched rectilinear shapes inflate boundary length, which means more crossings, more shifters, and worse congestion. Size the region to the domain's cell area plus headroom for special cells and switch fabric — too tight and the placer overflows the fence; too loose and you waste die and lengthen wires.
• Pin placement at borders. Place the region's interface pins on the edge nearest the blocks they talk to, so crossing signals take short paths through the boundary cells. Scattering interface pins around the perimeter forces long detours and aggravates congestion.
• Congestion at boundaries. Borders concentrate level shifters, isolation cells, and the nets feeding them, so routing demand spikes there. Reserve routing resource and avoid stacking other blockages against a busy border.
• Special-cell rings and rows. Many flows place a ring or row of boundary cells (level shifters, isolation, and sometimes always-on buffers) around or along the region edge. Plan rows that carry the correct rails for those cells — frequently an always-on rail — before detailed placement begins.

A Worked Conceptual Example: Two Voltage Areas

Suppose a design has a core cluster u_core that must run at the top rail, and a peripheral subsystem u_peri that can run reduced and be powered down. We first express the logical intent — two power domains — then bind each to a physical voltage area. The commands below use generic, vendorneutral syntax in the spirit of the UPF/CPF model. First, declare the logical power domains and their supplies:

# Logical intent: two power domains
create_power_domain PD_CORE -instances {u_core}
create_power_domain PD_PERI -instances {u_peri} -switchable
# Associate each domain with a primary supply net
set_domain_supply PD_CORE -primary VDD_HIGH -ground VSS
set_domain_supply PD_PERI -primary VDD_LOW  -ground VSS
# Border rules: shifters on voltage crossings, isolation on the
# switchable domain's outputs
set_level_shifter -domain PD_PERI -applies_to crossings -location border
set_isolation     -domain PD_PERI -applies_to outputs   \
-clamp 0 -enable iso_en -supply VDD_AON

Next, realize the intent physically by fencing each domain into a region and binding its rail. Coordinates are illustrative:

# Physical realization: voltage areas on the floorplan
create_voltage_area VA_CORE -domain PD_CORE \
-region {{0 0} {600 600}} -rail VDD_HIGH
create_voltage_area VA_PERI -domain PD_PERI \
-region {{620 0} {1000 400}} -rail VDD_LOW
# Reserve a border row on the always-on rail for shifters/isolation
create_boundary_row -between {VA_CORE VA_PERI} -rail VDD_AON \
-cells {level_shifter isolation}

Finally, a couple of sanity checks you would run before trusting the floorplan — the kind of verification that separates a clean MSV handoff from a respin:

# Verify no domain cell escaped its voltage area
check_voltage_area -domain PD_PERI -report stray_cells
# Verify every voltage crossing has a shifter, and every output of
# the switchable domain has isolation
check_crossings -level_shifter -isolation -report missing

The flow of intent here is the whole point: logic is grouped ( create_power_domain ), rules for its borders are stated, geometry is assigned ( create_voltage_area ), and then you verify the physical result honors the logical intent.

Common Pitfalls

Domain cells placed outside their area. The placer puts a PD_PERI cell in the gap between regions or inside VA_CORE . Now that cell is wired to the wrong rail — under-driven, over-driven, or simply unisolated when its real domain shuts off. Always fence the placement with hard region constraints and run a stray-cell check. Missing border shifters or isolation. A crossing was added late (an ECO net, a clock, a debug signal) and slipped past the boundary rules. Low-to-high crossings without a shifter cause static current and logic failure; un-isolated outputs of a switchable region corrupt live neighbors at shutdown. Re-run crossing checks after every netlist change, not just once. Voltage-area overlap. Two regions defined with overlapping coordinates leave the tool to guess which rail owns the shared sites — producing rail shorts or cells on the wrong supply. Keep regions disjoint (except for deliberate, properly handled nesting), and check geometry for overlap explicitly. Always-on cells on the wrong rail. Isolation and switch-enable cells placed on a switchable rail will die exactly when they are needed. Confirm every boundary and control cell sits on a genuine alwayson supply.

Interview Q&A

logical grouping of instances that share supply intent — same supply, isolation, retention, and shutdown behavior — declared in the power-intent file (UPF/CPF). A voltage area is the physical floorplan region that realizes that intent: a fenced set of placement rows wired to the domain's rail. Typically one domain maps to one voltage area, but a domain can span multiple regions if needed. Domains are logical and exist from synthesis on; voltage areas are physical and exist in place-androute.

a block's rail yields a quadratic dynamic-power reduction — about 36% saving for a 20% voltage cut. The cost is reduced drive strength and hence slower gates, so only blocks with timing slack can be moved to a lower rail. MSV also adds level shifters, isolation cells, multiple rails, and floorplan complexity, so the saving must justify the boundary overhead.

required whenever a signal crosses between two different voltages — especially low-to-high, where the receiver may not switch fully without one. An isolation cell is required whenever a signal leaves a region that can be powered down while the receiver stays live, clamping the floating output to a safe value. A crossing that is both lower-voltage and switchable needs both, sometimes in a combined

enable-level-shifter cell. Critically, isolation cells must be on an always-on supply so they function during shutdown.

physically embedded inside another — most commonly a small always-on retention island inside a larger switchable region, letting a few state-holding cells survive while the surrounding logic powers down. It saves wake-up time and avoids reloading state, but it complicates rail planning (threading the always-on supply into the island without shorting the switchable rail) and adds a second set of boundary crossing rules at the inner edge.

Key Takeaways

• Dynamic power scales with V², so matching each block's rail to its real performance need is the highest-leverage low-power technique available.
• A power domain is logical supply intent (UPF/CPF); a voltage area is its physical floorplan realization. Keep the distinction crisp and keep every domain cell inside its region.
• Voltage-boundary rules are non-negotiable: level shifters on voltage crossings, isolation cells on outputs of switchable regions, and both where a crossing is lower-voltage and switchable.
• Isolation and switch-control cells must sit on an always-on rail so they work precisely when a region is dark.
• Floorplan voltage areas as compact, disjoint, convex regions; cluster interface pins at the nearest border; reserve routing and special-cell rows for the congestion-prone boundaries.
• The three classic MSV bugs are cells escaping their area, missing border shifters/isolation, and overlapping voltage areas — guard against all three with explicit post-floorplan checks.