Static Timing Analysis
STA fundamentals — cell delay, interconnect, setup/hold, MCMM, OCV, noise, IR-drop and sign-off
28 chapters · All content free to read
- Ch 1What STA Is & Why It Replaced Simulation
- Ch 2Cell Delay, Slew & the Timing Library
- Ch 3Interconnect Delay & RC Parasitics
- Ch 4Timing Paths, Arrival/Required & Slack
- Ch 5Setup and Hold Checks
- Ch 6Clocks: Latency, Uncertainty, Skew & Jitter
- Ch 7Constraining a Design (the SDC Contract)
- Ch 8Timing Exceptions
- Ch 9Operating Conditions, PVT Corners & Derating
- Ch 10On-Chip Variation (OCV/AOCV/POCV) & CPPR
- Ch 11Multi-Corner Multi-Mode (MCMM) Analysis
- Ch 12Crosstalk & Signal Integrity in STA
- Ch 13Special Checks: Latches, Gating, CDC
- Ch 14Running STA, Reading Reports & Sign-off
- Ch 15Combinational Timing & Multi-Input Cell Arcs
- Ch 16Advanced Clocking: Generated, Divided & Gated
- Ch 17Multi-Clock Timing & Phase Relationships
- Ch 18Asynchronous Crossings & Metastability
- Ch 19Multicycle, Half-Cycle & Edge-Selection Cases
- Ch 20Latch-Based Timing & Time Borrowing
- Ch 21Advanced Variation: AOCV, POCV & Derate Strategy
- Ch 22Crosstalk & Noise: A Deep Dive
- Ch 23Power-Aware & Multivoltage STA
- Ch 24Hierarchical STA & Timing Models
- Ch 25Supply Noise (IR-Drop) & EM Effects on Timing
- Ch 26Worked STA Debug Scenarios
- Ch 27Interview Q&A Bank — Fundamentals
- Ch 28Interview Q&A Bank — Advanced
ChipBuddy
← Home