Design Constraints (SDC)
Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup
50 chapters · All content free to read
- Ch 1Why Timing Constraints Exist
- Ch 2The Synthesis & Timing Flow
- Ch 3Timing Analysis Basics — Paths, Setup & Hold
- Ch 4The Constraint Language — Tcl & SDC
- Ch 5Defining Clocks
- Ch 6Generated & Derived Clocks
- Ch 7Clock Groups & Relationships
- Ch 8Clock Latency, Uncertainty & Jitter
- Ch 9Input & Output Delays
- Ch 10Completing Port Constraints — Drive, Load & Transition
- Ch 11False Paths
- Ch 12Multicycle Paths
- Ch 13Point-to-Point & Combinational Delays
- Ch 14Modal Analysis — Multi-Mode Multi-Corner
- Ch 15Managing & Reusing Constraints
- Ch 16Miscellaneous Constraints — Case Analysis, DRC & Ideal Nets
- Ch 17FPGA Constraint Extensions
- Ch 18Clock Waveforms & Duty Cycle
- Ch 19Multi-Clock Domains & Phase Relationships
- Ch 20Clock Gating & Gated-Clock Constraints
- Ch 21Generated Clocks — Advanced Cases
- Ch 22Virtual Clocks & I/O Timing Budgets
- Ch 23Source-Synchronous Interfaces
- Ch 24System-Synchronous & Common-Clock Interfaces
- Ch 25Double-Data-Rate (DDR) Interface Constraints
- Ch 26Asynchronous Crossings & CDC Constraints
- Ch 27Clock Groups in Depth
- Ch 28Clock Latency — Source vs Network
- Ch 29Clock Uncertainty & Margins
- Ch 30Input & Output Delay — Multiple Clocks & Min/Max
- Ch 31Driving Cell & Load Modeling
- Ch 32Design-Rule Constraints — Transition, Cap & Fanout
- Ch 33False Paths — Advanced & Pitfalls
- Ch 34Multicycle Paths — Edge Mechanics
- Ch 35Point-to-Point & Combinational Delays
- Ch 36Case Analysis & Mode Configuration
- Ch 37Disabling Timing Arcs & Breaking Loops
- Ch 38Operating Conditions & PVT Corners
- Ch 39On-Chip Variation & Timing Derate
- Ch 40MMMC Scenario Construction
- Ch 41Hierarchical Constraints & Block Models
- Ch 42Block-Level I/O Budgeting
- Ch 43Constraint Reuse & IP Integration
- Ch 44Reset, Recovery & Removal Constraints
- Ch 45Latch-Based Timing & Time Borrowing
- Ch 46Half-Cycle Paths & Edge Selection
- Ch 47Constraint Validation & Linting
- Ch 48Constraint Quality & Common Mistakes
- Ch 49Quick Reference & Worked Examples
- Ch 50Interview Q&A Bank
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