CMOS VLSI Design
Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test
47 chapters · All content free to read
- Ch 1The MOS Transistor — How It Switches
- Ch 2Building CMOS Logic Gates
- Ch 3The CMOS Inverter — Transfer Curve & Noise Margins
- Ch 4Switching Speed & the RC Delay Model
- Ch 5Power — Dynamic, Short-Circuit & Leakage
- Ch 6Combinational Circuit Families
- Ch 7Sequential Circuits — Latches & Flip-Flops
- Ch 8Interconnect — Wires, R, C & Delay
- Ch 9Fabrication & Layout Basics
- Ch 10Memory — SRAM & DRAM
- Ch 11Datapath Building Blocks
- Ch 12Scaling, Reliability & Variation
- Ch 13Testing & Design-for-Test
- Ch 14Quick Reference & Interview Q&A
- Ch 15MOS Device Physics — A Deeper Look
- Ch 16Logical Effort & Gate Sizing
- Ch 17Interconnect & Repeaters — Deep Dive
- Ch 18Adders — Generate, Propagate & Trees
- Ch 19Multipliers & Booth Encoding
- Ch 20Clocking, Skew & Pipelining
- Ch 21ALU, Shifters & Comparators
- Ch 22I/O Circuits & ESD Protection
- Ch 23Low-Power Design Techniques
- Ch 24Clock Generation — PLL & DLL
- Ch 25Packaging & Power Delivery
- Ch 26Yield, Defects & Test — Deep Dive
- Ch 27Design Flow — RTL to GDSII
- Ch 28FinFET & Advanced Devices
- Ch 29Static vs Dynamic Logic
- Ch 30SRAM Design — Deep Dive
- Ch 31Nonvolatile & Emerging Memory
- Ch 32Signal Integrity & Crosstalk
- Ch 33Electromigration & Wire Reliability
- Ch 34Thermal Design & Hot Spots
- Ch 35Analog Basics for Digital Designers
- Ch 36Verification & Timing Closure
- Ch 37Standard-Cell Libraries & Characterization
- Ch 38Floorplanning & Placement
- Ch 39Routing, Vias & Design Rules
- Ch 40Finite State Machines & Control Logic
- Ch 41Interview Q&A Bank — Devices & Circuits
- Ch 42Interview Q&A Bank — Devices & Circuits
- Ch 43Interview Q&A Bank — Physical & Systems
- Ch 44Interview Q&A Bank — Physical & Systems
- Ch 45Numerical Problems & Worked Solutions
- Ch 46Numerical Problems & Worked Solutions
- Ch 47Glossary of CMOS Terms
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