Prerequisites for Routing

Global routing, track assignment, detail routing, DRC convergence, SI and postroute optimization

Routing is the stage where the abstract netlist finally becomes physical metal. But the router is only as good as the database you hand it. Think of the detail router inside the routing tool (the router) as an extremely literal, extremely fast contractor: it will build exactly what the design rules, the floorplan, and the constraints describe — and it will faithfully reproduce every mistake you left in place. Before you ever type a route command, a long list of conditions must already be true. This chapter walks through those prerequisites, why each one matters, and how to verify them so that routing produces something you can actually sign off.

Why Prerequisites Decide the Outcome

The router does not invent missing information. If a layer's track pitch is wrong, every wire on that layer inherits the error. If the clock tree was never built, the router will happily connect clock pins with ordinary signal wires that have no skew control and no shielding. If the power grid is incomplete, you may not even have a place to drop down to tap cells, and antenna fixing will fail because there is nowhere to insert a diode connection. Garbage in, garbage out is not a slogan here — it is a measurable, schedule-killing reality. A clean prerequisite list is the cheapest insurance you can buy against a multi-day debug spiral after the route.

Library and Technology Prerequisites

Everything physical that the router does is governed by the technology data. This is the foundation, and if the foundation is wrong, nothing above it can be trusted.

LEF and the Technology File

The router needs an abstract view of every cell (the LEF, or its equivalent inside the routing tool NDM library) and a description of the metal stack (the technology file). From the technology data the tool learns which layers exist, their preferred routing direction, minimum width and spacing, pitch, and which vias connect adjacent layers. Without correct layer definitions the router cannot even build a routing grid. A few specifics that routing depends on directly:

• Routing layers and directions. Each metal layer is normally assigned a preferred direction — horizontal or vertical — alternating up the stack. The router prefers wires in the preferred direction and uses the orthogonal direction sparingly for jogs.
• Tracks and pitch. Tracks are the legal centerlines on which wires may sit. Pitch is the spacing between tracks, derived from minimum width plus minimum spacing.
• Via definitions. Every layer transition needs a via. Cut layers, enclosure rules, and via arrays must all be defined, including the wide-metal and stacked-via variants the router may need.
• Design rules. Minimum spacing, end-of-line spacing, parallel-run length rules, minimum area, and more. Modern nodes add a thick book of complex rules that the router must honor on the fly.

RC and DFM Data: RC technology / TLU+ and library-model

Connectivity is only half the story; the router and the optimizer also need to know what each wire costs electrically. That comes from the extraction technology data — historically the RC technology, compiled into TLU+ files (a captable/QRC tech in newer flows). These provide the resistance and capacitance per unit length per layer, allowing the tool to estimate timing on partially routed nets and to make trade-offs during postroute optimization.

DFM and manufacturability data also belong here. Information used for wire spreading, via doubling, and other yield-friendly behaviors lets the router improve manufacturability without your having to micromanage it. The library-model, where used, carries additional cell-level modeling. The takeaway: if your parasitic tech files are missing or mismatched to the metal stack, postroute timing will be fiction.

rules

Design rules Spacing, width, EOL, min- DRC explosion after route

TLU+ / QRC tech (from RC Per-layer R and C Bogus parasitics and timing

DFM / yield data Spreading, via doubling rules Lower yield, weaker manufacturability With the technology in place, the design itself must reach a specific state of readiness. Routing is a late stage; it assumes that several earlier milestones are complete and clean.

Legal Placement

Every standard cell and macro must be legally placed: on-site, on-row, non-overlapping, and respecting placement blockages and edge spacing rules. The router routes to pin locations as they physically sit. If cells overlap or sit off-grid, pin access becomes impossible and the router will leave shorts or opens it cannot resolve. Run a legality check and confirm zero violations before routing. Illegal placement is the single most common reason a "router problem" turns out not to be the router's fault at all.

Completed Clock Tree (CTS)

The clock tree must be built before signal routing. CTS inserts buffers and inverters, balances skew, and defines the clock network topology. Equally important, CTS hands routing a set of clock nets that often carry special routing requirements: non-default rules for width and spacing, shielding, and sometimes dedicated layers. If you route before CTS, the clock pins get connected as plain signals, your skew and insertion delay are meaningless, and you will rip everything up and start over. In a typical the routing tool flow, clock nets are routed first (often with their NDRs and shields) and then signal routing fills in around them.

Power and Ground Network

The PG network — rings around the core and macros, stripes across the floorplan, and the standardcell rails — must be built and connected before signal routing. Three reasons:

1. 1. The router treats PG metal as a routing obstacle, so it must exist for the router to route around it

correctly.

1. 2. Cells draw power from the rails; if rails are missing, you have connectivity holes the router cannot

fix.

1. 3. Antenna repair frequently relies on diode insertion and jumper-to-upper-layer moves that assume a

working grid. A PG network that is incomplete or has open stripes leads to IR-drop problems that surface far too late, and to a router that is making decisions around a grid that will later change.

Clocks Defined, Propagated, and Constraints Loaded

The timing setup must be real before routing, because postroute optimization is timing-driven. That means:

• Clocks created and propagated. Use propagated (not ideal) clocks for postroute work so the tool sees real insertion delay from the built tree.
• SDC loaded. Clock definitions, I/O delays, false paths, multicycle paths, and exceptions all shape what the optimizer treats as critical. A missing exception can send the optimizer chasing a path that does not exist, wasting area and runtime.
• Scenarios and corners set up. Modern signoff is multi-corner, multi-mode. The active scenarios — combinations of process corner, voltage, temperature, and operating mode — must be defined and enabled so the router and optimizer trade off correctly across them. Routing for the typical corner alone and discovering setup or hold failures at the slow or fast corner later is a classic, avoidable mistake.

The physical canvas the router draws on must be defined and clean.

Tracks and the Routing Grid

Tracks define where wires may legally run on each layer. They are usually generated from the technology pitch and aligned so that pins and standard-cell rails land on the grid. If tracks are missing on a layer, the router simply will not use that layer; if they are misaligned, pin access suffers and via count balloons. Verify tracks exist on every routing layer you intend to use and that the minimum and maximum routing layers are set to match your floorplan strategy.

# Establish and inspect the routing grid before routing
# Restrict routing to the intended layer range
set_ignored_layers -min_routing_layer M2 -max_routing_layer M7
# Verify tracks are present on the routing layers
report_track
# Make sure routing layer direction and preference are as expected
report_design -routing

Blockages and Keepouts

Routing blockages tell the router where it may not place metal — over sensitive analog regions, in macro halos, or in reserved channels. Keepout margins around macros prevent the router from jamming wires against macro pins where access is poor. These must be in place before routing so the router plans around them from the start. Adding blockages after a route forces a rip-up and reroute, which costs runtime and can perturb timing that was already closed.

The Pre-Route Checklist

Before launching detail routing, walk this checklist. It captures the conditions that most often bite teams in practice.

1. Placement Legality

Confirm legalization is clean. No overlaps, everything on-row and on-site, blockages respected. A single off-grid macro can sabotage an entire region.

2. Antenna Setup

Antenna rules and the repair strategy must be configured. Decide up front whether you will fix antenna violations by layer hopping (jumping to a higher layer) or by diode insertion, and make sure antenna diode cells are available in the library and not set to dont-use. Antenna setup is easy to forget and painful to retrofit, because antenna fixes change routing topology.

3. NDR Rules Available

Non-default rules for clocks, high-speed nets, and shielded nets must be defined and bound to the right nets or net groups. If the NDR exists but is never applied, the router uses default rules and your critical nets lose their wider, better-spaced wires.

4. Congestion Sanity

Run a global route or early congestion estimate. If the map shows deep red hotspots before detail routing, fix the floorplan or placement first — do not ask the detail router to perform a miracle in a region that is already over capacity. Congestion problems are placement problems wearing a routing costume.

# Pre-route congestion sanity via global route
global_route
report_congestion -routing_stage global
# Confirm NDRs exist and are bound to clock nets
report_routing_rules
# Check antenna setup and that diode cells are usable
report_lib_cell -objects [get_lib_cells */*ANTENNA*]

5. Constraints and Corners

Re-confirm SDC is loaded without errors, clocks are propagated, and all signoff scenarios are active. This overlaps with the timing prerequisites above, but it is worth a final explicit check because a quietly disabled hold scenario can pass routing and fail signoff.

It is tempting, under schedule pressure, to start routing on a design that is "mostly ready." The failure modes are predictable and expensive:

• Route before CTS: clock nets routed as ordinary signals; full rip-up after the tree is built; wasted days.
• Incomplete PG network: IR-drop surprises, connectivity holes, antenna fixes with nowhere to land.
• Illegal placement: pin access failures producing unresolvable shorts and opens the router gets blamed for.
• Missing or mismatched TLU+ / QRC tech: postroute timing that looks fine in the tool and fails at signoff extraction.
• Unset corners or disabled scenarios: a chip that is timing-clean at one corner and broken at another.

• No NDRs / no antenna setup: critical nets under-protected; antenna DRCs that force topology- changing fixes late. The common thread is that every one of these defects is cheap to catch before routing and very expensive to catch after. A disciplined prerequisite pass, codified as a script you run every time, is the difference between a route you trust and a route you babysit.

Interview Q&A

builds the physical clock tree — inserting buffers and inverters, balancing skew, and defining the clock topology with its special routing rules. Routing assumes those clock nets exist with their NDRs and shields. If you route before CTS, clock pins get connected as plain signals with no skew control or shielding, your insertion delay and skew numbers are meaningless, and you must rip up and reroute once the tree is built. CTS is a hard gate before routing.

cell views it needs the technology file (layer directions, pitch, via and design rules) to build a legal routing grid, and it needs extraction data — TLU+ or a QRC tech compiled from the RC technology — to estimate per-layer resistance and capacitance. Without parasitic data, postroute optimization is timing-blind and its decisions are unreliable. DFM data additionally enables wire spreading and via doubling for better yield.

problem? Usually no. Congestion that shows up at the global stage almost always traces back to placement or floorplan — cells packed too tightly, poor macro placement creating narrow channels, or pin-dense regions. Asking the detail router to fix deep-red hotspots leads to detours, DRC violations, and timing degradation. The right move is to address placement or floorplan first, then route. Congestion is a placement problem in disguise.

afterward? Because antenna fixes change routing topology. The two main repairs — layer hopping to break up long same-layer antennas, and diode insertion — both alter the route or require usable diode cells in the library. If antenna rules and the repair strategy are not configured up front, the router cannot avoid or pre-plan for antenna issues, and you are forced into disruptive late fixes that can perturb timing you had already closed. Setting it up before routing lets the tool route antenna-aware from the start.

Key Takeaways

• The router faithfully builds whatever the tech data, floorplan, and constraints describe — including every defect. Garbage in, garbage out is literal.

• Library prerequisites: correct LEF/NDM views, a technology file with layers, tracks, vias, and design rules, plus TLU+/QRC parasitic data and DFM information for trustworthy timing and yield.
• Design prerequisites: legal placement, a completed clock tree, and a fully built and connected PG network (rings, stripes, rails).
• Timing prerequisites: clocks defined and propagated, SDC loaded cleanly, and all signoff scenarios and corners active so optimization trades off correctly.
• Canvas prerequisites: tracks and routing grid defined, layer range set, blockages and keepouts in place before the route, and NDRs defined and bound.
• Run a fixed pre-route checklist every time: legality, antenna setup, NDR availability, congestion sanity, and constraints/corners. Catching a missing prerequisite before routing is cheap; catching it after is a schedule hit.