Chapter 18 The 8051 Microcontroller

Number systems, Boolean algebra, logic gates, combinational circuits, flip-flops, counters, shift registers, memory and microprocessors

OUTLINE

18–1 The 8051 Family of Microcontrollers

18–2 8051 Architecture

18–3 Interfacing to External Memory

18–4 The 8051 Instruction Set

18–5 8051 Applications

18–6 Data Acquisition and Control System Application

18–7 Conclusion

OBJECTIVES

Upon completion of this chapter you should be able to do the following:

• Describe the advantages that a microcontroller has over a microprocessor for control applications.
• Describe the functional blocks within the 8051 microcontroller.
• Make comparisons between the different microcontrollers available within the 8051 family.
• Write the software instructions to read and write data to and from the I/O ports.
• Describe the use of the alternate functions on the I/O ports.
• Make the distinction between the internal and external data and code memory spaces.
• Use various addressing modes to access internal data memory and the Special Function Registers (SFRs).
• Interface an external EPROM and a RAM to the 8051.
• Use some of the more commonly used instructions of the 8051 instruction set.
• Write simple 8051 I/Os programs.
• Use the bit operations of the 8051.
• Understand program solutions to applications such as a keyboard decoder and analog-to-digital converter. *Chapter 18 is reprinted from Digital and Microprocessor Fundamentals: Theory and Applications, Fourth Edition; by William Kleitz, © 2003. Reprinted by permission of Pearson Education Inc., Upper Saddle River, NJ. †Visit the following sites for microcontroller trainers and downloadable software tools: www.acebus.com, www.bipom.com, www.elexp.com, www.emacinc.com, and www.8052.com

In the previous chapter you should have recognized several common components that are incorporated into most microprocessor-based system applications. These are the microprocessor, RAM, ROM (or EPROM), and parallel I/O ports. Microprocessor manufacturers have recognized this and over the years since the introduction of the 8085A have been developing a new line of microprocessors specifically designed for control applications. They are called microcontrollers. The microcontroller has the CPU, RAM, ROM, timer/counter, and parallel and serial I/O ports fabricated into a single IC. It is often called “a computer on a chip.” The CPU’s instruction set is improved for control applications and offers bit-oriented data manipulation, branching, and I/O, as well as multiply and divide instructions. The microcontroller is most efficiently used in systems that have a fixed program for a dedicated application. A microcontroller is used in a keyboard for a personal computer to scan and decode the keys. It is used in an automobile for sensing and controlling engine operation. Other dedicated applications such as microwave ovens, videocassette recorders, gas pumps, and automated teller machines use the microcontroller IC also. The previous chapters have provided a good background for understanding the microcontroller. The theory behind microprocessor buses, external memory, and I/O ports is necessary to utilize the features available on a microcontroller. In this chapter we’ll be introduced to one of the most widely used microcontrollers available: the

1. 8051. You’ll see several similarities between it and the 8085A-based systems previ-

ously discussed. You should appreciate the way that you were eased into microprocessor operational theory using the 8085A, but now you will see why the 8051 can be a much better solution to dedicated control applications. Most control applications require extensive I/O and need to work with individual bits. The 8051 addresses both of these needs by having 32 I/O lines and a CPU instruction set that handles single-bit I/O, bit manipulation, and bit checking.

18–1 The 8051 Family of Microcontrollers

The basic architectural structure of the 8051 is given in Figure 18–1. The block diagram gives us a good picture of the hardware included in the 8051 IC. For internal

memory it has a 4K * 8 ROM and a 128 * 8 RAM. It has two 16-bit counter/timers RXD (transmit and receive), and it also has four 8-bit parallel I/O ports (P0, P1, P2, P3). There is also an 8052 series of microcontrollers available that has an 8K ROM, 256 RAM, and three counter/timers. Other versions of the 8051 are the 8751, which has an internal EPROM for program storage in place of the ROM, and the 8031, which has no internal ROM, but instead accesses an external ROM or EPROM for program instructions. Table 18–1 summarizes the 8051 family of microcontrollers. Note that the 8052/8752/8032 series has an extra 4K of program space (except the 8032), double the RAM area, an extra timer/counter, and one additional interrupt source. All parts use the same CPU instruction set. The ROMless versions (8031 and 8032) are the least expensive parts but require an external ROM or EPROM such as a 2732 or 2764 for program storage.

18–2 8051 Architecture

To squeeze so many functions on a single chip, the designers had to develop an architecture that uses the same internal address spaces and external pins for more than one function. This technique is similar to that used by the 8085A for the multiplexed

AD0-AD7 lines.

◆ Figure 18–1 Block diagram of the 8051 microcontroller.

TABLE 18–1 The 8051 Family of Microcontrollers

The 8051 is a 40-pin IC. Thirty-two pins are needed for the four I/O ports. To provide for the other microcontroller control signals, most of those pins have alternate functions, which are described in this section. Also in this section, we see how the 8051 handles the overlapping address spaces used by internal memory, external memory, and the special function registers. The pin configuration for the 8051 is given in Figure 18–2.

Port 0

Port 0 is dual-purpose, serving as either an 8-bit bidirectional I/O port (P0.0–P0.7) or

the low-order multiplexed address/data bus (AD0-AD7). As an I/O port, it can sink up

(IOL = 3.2mA). The alternate port designations, AD0-AD7, are used to access exter-

memory. The AD lines are demultiplexed into A0-A7 and D0-D7 by using the ALE

Port 1

Port 1 is an 8-bit bidirectional I/O port that can sink or source up to 4 LS TTL loads.

(IOL = 1.6mA and IOH = -80mA.)

◆ Figure 18–2 The 8051 pin configuration.

Port 2

Port 2 is dual-purpose, serving as either an 8-bit bidirectional I/O port (P2.0–P2.7) or

as the high-order address bus (A8-A15) for access to external memory. As an I/O port address bus whenever reference to external memory is made.

Port 3

Port 3 is dual-purpose, serving as an 8-bit bidirectional I/O port that can sink or source up to 4 LS TTL loads or as special-purpose I/O to provide the functions listed in Table 18–2.

RST

Reset input. A HIGH on this pin resets the microcontroller.

ALE/ PROG

Address Latch Enable output pulse for latching the low-order byte of the address dur-

ing accesses to external memory. This pin is also the program pulse input (PROG) dur-

Program Store Enable is a read strobe for external program memory. It will be con-

code from an external memory IC. This pin also receives the 21-V programming supply voltage (VPP) for programming the EPROM parts.

XTAL1,XTAL2

Connections for a crystal or an external oscillator.

Address Spaces

The address spaces of the 8051 are divided into four distinct areas: internal data memory, external data memory, internal code memory, and external code memory (see

◆ Figure 18–3).

The 8051 allows for up to 64K of external data memory (RAM) and 64K of external code memory (ROM/EPROM). The only disadvantage of external memory, in addition to the additional circuitry, is that ports 0 and 2 get tied up for the address and data bus. The actual hardware interfacing for external memory are given later in this chapter. When the 8051 is first reset, the program counter starts at 0000H. This points to

LOW if using the ROMless (8031) version.

With EA tied HIGH, the first 4K of program instruction fetches are made from FFFFH) will automatically be made from the external code memory. If the application has a need for large amounts of data memory, then external data memory (RAM) can be used. I/O to external RAM can only be made by using one of the MOVX instructions. When executing a MOVX instruction, the 8051 knows that

you are referring to external RAM and issues the appropriate WR or RD signal. memory is better to use because it has a much faster response time and a broad spectrum of instructions to access it. Figure 18–3 shows two blocks of internal data memory. The first is the 128-byte RAM at address 00H to 7FH. The second is made up of the Special Function Registers (SFRs) at addresses 80H to FFH. Note that all addresses are only 1 byte wide, which allows for more efficient use of code space and faster access time. The use of the address space in the 128-byte RAM is detailed in

◆ Figure 18–4.

The first 32 locations are set aside for four banks of data registers (called register banks), giving the programmer the use of 32 separate registers. The registers within each bank are labeled R0 through R7. The bank that is presently in use is defined by the setting of the two “bank select bits” in the PSW (Program Status Word).

◆ Figure 18–4 Address space in the 128-byte internal data memory RAM.

locations. This meets the needs of control applications for a large number of ON/OFF bit flags, by providing 128 uniquely addressable bit locations. The last 80 locations are set aside for general-purpose data storage and stack operations. The Special Function Registers are maintained in the next 128 addresses in the internal data memory of the 8051 (address 80H to FFH). It contains registers that are required for software instruction execution as well as those used to service the special hardware features built into the 8051. Table 18–3 lists the SFRs and their addresses. The address of an SFR is also only 1 byte wide. However, instead of specifying the 1-byte hex address, you also have the option of addressing any SFR location by simply specifying its register name, like P0 or SP. Several of the SFRs are bit addressable. For example, to address bit 3 of the accumulator, you would use the address E0H.3 (or you could use ACC.3). The PSW is also bit addressable, having the bit addresses listed in Table 18–4. For example, to address the parity bit in the PSW, you would use the address D0H.0 (or you could use PSW.0).

TABLE 18–3 The Special Function Registers (SFRs) [Internal Data

aBit-addressable register.

Up to 64K of code memory (ROM/EPROM) and 64K of data memory (RAM) can be added to any of the 8051 family members. If you are using the 8031 (ROMless) part, then you have to use external code memory for storing your program instructions. As mentioned earlier, the alternate function of port 2 is to provide the high-order address

If you are interfacing to a general-purpose EPROM like the 2732, then the ALE

signal provided by the 8031 is used to demultiplex the AD0-AD7 lines via an address As you can see, two of the I/O ports are used up to provide the address and data

buses. The AD0-AD7 lines that are output on port 0 are demultiplexed by the ALE sig-

lier. The PSEN signal is asserted at the end of each instruction fetch cycle to enable the

The EA line is tied LOW so that the 8031 knows to fetch all program code from exter-

◆ Figure 18–5 Interfacing a 2732 EPROM to the ROMless 8031 microcontroller.

can be used. The 8155 RAM accepts the lines directly and uses the ALE to use 11 of the 8051 pins to interface to the 8155, but the 8155 provides an additional 22 I/O lines, giving us a net gain of 11. The addresses of the external RAM locations are 0000H to 00FFH, overlapping the addresses of the internal data memory. There is not a conflict, however, because all I/O to the external data memory is made using the MOVX instruction. The MOVX instruction ignores internal memory and, instead, activates the appropriate control sig-

nal, RD or WR via port 3. The LOW RD or WR signal allows the 8155 to send or

The I/O ports on the 8155 are accessed by making the IO/M line HIGH. This is (8000H or higher).

◆ Figure 18–6 Interfacing an 8155 RAM/IO/Timer to the 8051 microcontroller.

All the members of the 8051 family use the same instruction set. (The complete instruction set is given in the 8051 Instruction Set Summary in Appendix H.) Several new instructions in the 8051 make it especially well suited for control applications. The discussion that follows assumes that you are using a commercial assembler software package. Hand assembly of the 8051 instructions into executable machine code is very difficult and misses out on several of the very useful features available to the ASM51 programmer.

Addressing Modes

The instruction set provides several different means to address data memory locations. We’ll use the MOV instruction to illustrate several common addressing modes. For example, to move data into the accumulator, any of the following instructions could be used:

MOV A,Rn: Register addressing, the contents of register Rn (where n = 0-7) MOV A,@Ri: Indirect addressing, the contents of memory whose address is in

Ri (where i = 0 or 1) is moved to the accumulator. (Note: Only registers R0 and MOV A,20H: Direct addressing, move the contents of RAM location 20H to the accumulator. I/O ports can also be accessed as a direct address as shown in the following instruction. MOV A,P3: Direct addressing, move the contents of port 3 to the accumulator. Direct addressing allows you to specify the address by giving its actual hex address (e.g., B0H) or by giving its abbreviated name (e.g., P3), which is listed in the SFR table (Table 18–3). MOV A,#64H: Immediate constant, move the number 64H into the accumulator. In each of the previous instructions, the destination of the move was the accumulator. The destination in any of those instructions could also have been a register, a direct address location, or an indirect address location.

EXAMPLE 18–1

Write the 8051 instruction to perform each of the following operations. (a) Move the contents of the accumulator to register 5. (b) Move the contents of RAM memory location 42H to port 1. (c) Move the value at port 2 to register 3. (d) Send FFH to port 0. (e) Send the contents of RAM memory, whose address is in register 1, to port 3.

Solution:

(a) MOV R5,A (b) MOV P1,42H (c) MOV R3,P2

is because the ASM51 assembler requires that the first position of any hexadecimal number must be a numeric digit from 0 to 9.) (e) MOV P3,@R1

Program Branching Instructions

8051 assembly language provides several different ways to branch (jump) to various program segments within the 64K of code memory area. Below are some of the most useful jump instructions. JMP label (Unconditional jump): Program control passes to location label. The JMP instruction is converted by the ASM51 assembler into an absolute jump, (AJMP), a short jump (SJMP), or a long jump (LJMP), depending on the destination pointed to by label. JZ label (Jump if accumulator zero): Program control passes to location label if the accumulator equals zero. JNZ label (Jump if accumulator not zero): Program control passes to location label if the accumulator is not equal to zero. JB bit,label (Jump if bit set): Program control passes to location label if the specified bit, bit, is set. JNB bit,label (Jump if bit not set): Program control passes to location label if the specified bit, bit, is not set. DJNZ Rn,label (Decrement register and jump if not zero): Program control passes to location label if, after decrementing register Rn, the register is not

equal to zero (n = 0-7). equal): Program control passes to location label if register Rn is not equal to the immediate data #data. The compare can also be made to the accumulator by specifying A instead of Rn. CALL label (Call subroutine): Program control passes to location label. The return address is stored on the stack. The CALL instruction is converted by the ASM51 assembler into an absolute call, ACALL, or a long call, LCALL, depending on the destination pointed to by label. RET (Return): Program control is returned back to the instruction following the CALL instruction.

EXAMPLE 18–2

Write a program that continuously reads a byte from port 1 and writes it to port 0 until the byte read equals zero.

Solution:

etc.

Repeat Example 18–2, except stop the looping when the number 77H is read.

Solution:

etc.

EXAMPLE 18–4

Repeat Example 18–2, except stop the looping when bit 3 of port 2 is set.

Solution:

EXAMPLE 18–5

Write a program that will produce an output at port 0 that counts down from 80H to 00H.

Solution:

Logical and Bit Operations

The 8051 instruction set provides the basic logical operations (OR, AND, Ex-OR, and NOT), rotates (left or right, with or without carry), and bit operations (Clear, Set, and complement). The following list shows some of the most commonly used of those operations. ANL A,Rn (AND register to accumulator): Logically AND register Rn, bit by bit, with the accumulator and store the result in the accumulator. ANL A,#data (AND data byte to accumulator): Logically AND data byte #data, bit by bit, with the accumulator and store the result in the accumulator.

use the following instructions: ORL A,Rn (OR register to accumulator) ORL A,#data (OR data byte to accumulator) XRL A,Rn (Ex-OR register to accumulator) XRL A,#data (Ex-OR data byte to accumulator) The most commonly used instructions to operate on individual bits are as follows: CLR bit (Clear bit): Clear (reset to 0) the value of the bit located at address bit. SETB bit (Set bit): Set (set to 1) the value of the bit located at address bit. CPL bit (Complement bit): Complement the value of the bit located at address bit. The rotate commands available to the 8051 programmer are as follows: RL A (Rotate accumulator left): Rotate the 8 bits of the accumulator one position to the left. RLC A (Rotate accumulator left through carry): Rotate the 9 bits of the accumulator including carry one position to the left. RR A (Rotate accumulator right): Rotate the 8 bits of the accumulator one position to the right. RRC A (Rotate accumulator right through carry): Rotate the 9 bits of the accumulator including carry one position to the right. The following examples illustrate the use of the logical and bit operations.

EXAMPLE 18–6

Determine the contents of the accumulator after the execution of the following program segments.

Solution:

A = 00111100 R4 = 01100110

AANDR4 = 00100100 = 24H Answer

Solution:

A = 0011 1111 7CH = 0111 1100

A EX@OR 7CH = 0100 0011 = 43H Answer

RR A ; Rotate right A = 1010 0011 Rotate right

A = 1101 0001 Answer

Solution:

Assume carry = 0 initially A = 1100 0011 Rotate left through carry

A = 1000 0110, carry = 1 Answer

EXAMPLE 18–7

Use the SETB, CLR, and CPL instructions to do the following operations: (a) Clear bit 7 of the accumulator. (b) Output a 1 on bit 0 of port 3. (c) Complement the parity flag (bit 0 of the PSW).

Solution:

(a) CLR ACC.7 (Note: According to Table 18–3, the symbol for the direct address of the accumulator is ACC.) (b) SETB P3.0 (c) CPL PSW.0

EXAMPLE 18–8

Describe the activity at the output of port 0 during the execution of the following program segment: MOV R7,#0AH MOV P0,#00H

LOOP: CPL P0.7 Solution: Register 7 is used as a loop counter with the initial value of 10 (0AH). Each time that the complement instruction (CPL) is executed, bit 7 will toggle to its opposite state. Toggling bit 7 ten times will create a waveform with five positive pulses.

The 8051 is capable of all the basic arithmetic functions: addition, subtraction, incrementing, decrementing, multiplication, and division. The following list outlines the most commonly used forms of the arithmetic instructions. ADD A,Rn (Add register to accumulator): Add the contents of register Rn

(where n = 0-7) to the accumulator and place the result in the accumulator. the accumulator and place the result in the accumulator. SUBB A,Rn (Subtract register from accumulator with borrow): Subtract the contents of register Rn and borrow (carry flag) from the accumulator and place the result in the accumulator. SUBB A,#data (Subtract immediate data from accumulator with borrow): Subtract the value of #data and borrow (carry flag) from the accumulator and place the result in the accumulator. INC A (Increment accumulator) INC Rn (Increment register) DEC A (Decrement accumulator) DEC Rn (Decrement register) MUL AB (Multiply A times B): Multiply the value in the accumulator times the value in the B register. The low-order byte of the 16-bit product is left in the accumulator and the high-order byte is placed in register B. DIV AB (Divide A by B): Divide the value in the accumulator by the value in the B register. The accumulator receives the quotient and register B receives the remainder. DA A (Decimal adjust accumulator): Adjust the value in the accumulator, resulting from an addition, into two BCD digits.

The following examples illustrate the use of arithmetic instructions.

EXAMPLE 18–9

Add the value being input at port 1 to the value at port 2 and send the result to port 3.

Solution:

EXAMPLE 18–10

Multiply the value being input at port 0 times the value at port 1 and send the result to ports 3 and 2 (high order/low order).

Having bit-handling instructions and built-in I/O makes the 8051 a good choice for data acquisition and control applications. In this section we look at a few applications that illustrate how we can utilize these new features to simplify our program solutions.

Instruction Timing

The 8051 circuitry that we looked at earlier was driven with a 12-MHz crystal. The 12 MHz is a convenient choice because each instruction machine cycle takes 12 clock periods

to complete. This means that one machine cycle takes 1ms. All 8051 instructions are DIV, which take four. The oscillator periods for each instruction are given in the 8051 Instruction Set Summary (Appendix H). For example, the MOV A,Rn instruction

requires 12 oscillator periods to complete, which will take 1ms [12 * (1/12MHz)]. Knowing the time duration of each instruction, we can write accurate time delays for our applications programs. Writing counter/loop programs is much easier now, with the introduction of the DJNZ and the CJNE instructions. Table 18–5 and Figure 18–7 show a time-delay program that we could call as a subroutine from an applications program.

ter 0 at 00H, the first time DJNZ R0,LOOP is executed, R0 will become FFH. The program will loop within that same instruction 255 more times until R0 equals 0. At that point, control drops down to the next DJNZ, which functions as an outer loop as shown in the flowchart.

The R0 (inner) loop will take 512 s to complete. The R1 (outer) loop exe- m second. A third loop, using R2, could be added to increase the time by another factor of 256.

◆ Figure 18–7 Flowchart for the time-delay subroutine of Table 18–5.

EXAMPLE 18–12

Write a program that will decode the hexadecimal keyboard shown in

◆ Figure 18–8.

Solution:

;

;

;

◆ Figure 18–8 Keyboard interface to an 8051.

Explanation: The keyboard is wired as a 4 * 4 row–column matrix. order is connected to the columns. The rows and columns are held HIGH

with the 10@k� pull-up resistors. Because the I/O ports of the 8051 can nique to scan a keyboard than we would use with the 8085A. To determine the row of a depressed key, we drive all of the columns LOW and all of the rows HIGH by executing the instruction MOV P0,#0FH. The HIGH on the rows is actually a float state, allowing the rows to be read. The next series of instructions in the ROWRD subroutine read each row to determine the row number that is LOW, if any. If, for example, key 5 is depressed, then row 1 will be LOW and the other three rows will be HIGH. Now that we know the row, we must next determine the column. The instruction MOV P0,#0F0H will drive the rows LOW and float the columns. If the number 5 key is still depressed, column 1 will be LOW. The last subroutine converts the row–column combination to the numeric value of the key pressed. Rows 0, 1, 2, and 3 have weighting factors of 0, 4, 8, and 12, respectively, and columns 0, 1, 2, and 3 have weighting factors of 0, 1, 2, and 3, respectively. Knowing that, the CONVRT subroutine uses the following formula to determine the numeric value of the key pressed: Keypressed = row * 4 + column

EXAMPLE 18–13

◆ Figure 18–9 shows how an ADC0801 (or ADC0804) is interfaced to an

1. 8051. Write a program that takes care of the handshaking requirements for

SC and EOC to complete an analog-to-digital conversion.

◆ Figure 18–9 Interfacing an analog-to-digital converter to an 8051.

Solution:

Explanation: The I/O ports are in the float condition after the initial reset of the 8051. They must be floating to be used as inputs. The first two instructions in this program write 1s to ports 1 and 0, which make them float just in case they had 0s in them from a previous step in the program.

To start the conversion process, bit 6 of port 0 (SC) is pulsed LOW then

if-bit-set instruction (JB) then monitors bit 7 of port 0 (EOC) and remains 1 is read into register 0, which is used to hold the ADC result.

18–6 Data Acquisition and Control System Application

The object of this section is to implement the 8051-based data acquisition and control system shown in Figure 18–10. Three modules are discussed using several external transducers and instruments as follows:

◆ Figure 18–10 Modular 8051-based data acquisition and control application.

1. 1. ADC module with hex display of the output.
2. 2. DAC module with hex display of the input.
3. 3. 8051 microcontroller module with connection points for (1) and (2).

Assembly-language software will be written and stored on an EPROM connected to the 8051. This software will exercise the ADC/DAC modules and perform other I/O functions. One of the outcomes of these designs is for their use in colleges for teaching the concepts of data acquisition and control, so careful attention will be paid to the cost, durability, and ease of reproduction of each module.

Hardware

The 8051 Microcontroller Module The 8051 microcontroller module is shown in ule are input and output buffers, an address latch, and an EPROM interface. In Figure 18–11, the microcontroller used is the 8031, which is a subset of the

1. 8051. The 8031 differs in that it is the ROM-less part. Instead of using the 8051, which

has an internal mask-programmable ROM, we use the 8031 and interface an EPROM to it to supply our program statements. The 8031 will be run with a 12-MHz crystal. This was chosen because most of the instructions take 12 clock periods to execute. This way, accurate timing can be

developed based on 1@ms instruction execution time. required to access the EPROM comes from the 8 bits provided from port 0 and the 4 bits provided from port 2. The data output from the EPROM are sent back into the microcontroller via port 0. Because port 0 has a dual purpose (i.e., address and data), a control signal from the ALE line is used to tell the address latch when port 0 has valid

addresses and when it has data. Also, the EA signal is grounded, which signifies that the microcontroller is ready to read data from the EPROM. This LOW control signal is

attached to the OE line of the 2732 EPROM, which changes the outputs at D0 through reads the data.

Hardware reset is provided at pin 9 via the R-C circuit of R1 – C3. At power-up the HIGH-to-LOW level for PIN 9 to be reset. Resetting can also be accomplished with the push-button, which shorts the 5-V supply directly to pin 9 any time you want to have a user reset. Two eight-bit I/Os are provided via port 1 and port 3. In this circuit, port 1 is used as an output port capable of sinking or sourcing up to four LSTTL loads. This is equivalent to a sink current of approximately 1.6 mA, which is normally not enough to drive loads such as LED indicators. Because of this, the 74LS244 (U1) is used as an output buffer. The 74LS244 can sink 24 mA and source 15 mA. The outputs of this buffer are always enabled by grounding pins 1 and 19. This way, whatever appears at port 1 will immediately be available to the LEDs. The LEDs are connected as active-LOW by pro-

viding a series 270 ohm resistor to the 5-V supply. When any of the outputs of U1 go +

8051 Microcontroller with input/output.

on this module so that other devices can be driven from this port at the same time that the LEDs are being activated. In this circuit, port 3 is used for input. The 8-bit DIP switch is connected to port 3 in conjunction with the 10K DIP pack. Therefore, each of the bits of port 3 is normally HIGH via a 10K pull-up. They are made LOW any time one of the DIP switches is closed. An input socket is also provided at this port so that external digital inputs can be input to port 3. To use the input socket, all eight of the DIP switches must be in their open position so that the devices driving the input socket can drive the appropriate line LOW or HIGH without a conflict with the LOW from the DIP switch. The 74LS373 is an octal transparent latch used as an address demultiplexer. Data entered at the D inputs are transferred into the Q outputs whenever the LE input is HIGH. The data at the D inputs are latched when the LE goes LOW. This address latch is used to demultiplex port 0s address/data information. When port 0 has valid address information, the ALE line is pulsed HIGH. This causes the address latch to grab hold of the information on port 0 and pass it through to the Qs and latch onto it. After the addresses from port 0 are latched, the port is then placed in the float condition so that it can be used to receive the data from the EPROM as the PSEN line is pulsed LOW.

The LOW pulse on the PSEN line activates the active-LOW OE on the EPROM, which microcontroller, where they are used as program instructions.

The ADC Interface Module The heart of the ADC interface module (Figure 18–12) and can be directly interfaced to a microcontroller. The object of this interface module

is to convert analog quantities brought into Vin(+) into 8-bit digital outputs. The digital microcontroller module. They are also connected to the 2-digit hex display so that you can constantly monitor the 8-bit values that were converted.

equals approximately 606 kHz. Because this is a successive approximation ADC we can assume that the conversion will take place in 10 to 12 clock periods, which provides a conversion time of about 20 ms. The chip select (CS) pin on U1 is connected to ground so that the chip is always activated. The RD pin is an active-LOW output enable. This is connected to ground

has completed its conversion, it issues a LOW pulse on the INTR line [also known as

end-of-conversion (EOC) ], which will be read by the microcontroller to determine if

2.56 V. This way, with a Vref of 2.56 V, and an ADC that has a maximum number of steps of 256, the change in the output will be 1 bit change or 1 binary step for every 10 mV of input change. This provides a convenient conversion for the linear temperature sensor (T1) because T1 provides a 10 mV change for every degree Celsius. It also makes the calculations for the linear phototransistor sensor much simpler.

The DAC Interface Module The heart of the DAC interface module (Figure 18–13)

verted are brought into the A8-A1 digital input side with A1 receiving the MSB. The

The ADC 0804 interface module.

The MC1408 DAC interface module.

this current-to-voltage conversion, a 741 op amp is used. The current at Io is drawn

ratio of the analog Vout to the binary input is proportional to the ratio of the maximum analog Vout to the maximum binary input (15 V maximum divided by 256 maximum).

(Because the supply on the op amp is ; 15V, we will never be able to achieve 15 V A two-digit hexadecimal display is connected directly to the input to the DAC chip. This provides a way to monitor the binary input at any time.

Applications

Three separate applications are used to exercise the three modules. Each of these applications are controlled by the microcontroller and will read analog input values with the ADC and output analog values with the DAC.

Celsius Thermometer The Celsius thermometer application is shown in Figure to the ADC and display a binary coded decimal (BCD) output of the temperature. The LM35 linear temperature sensor is used to measure the temperature. It outputs 10 mV for every degree Celsius. This millivolt value is converted by the ADC into an 8-bit binary string, which is displayed on the hex display and also input to the microcontroller. Because the Vref on the ADC is set at 2.56 V, the output of the ADC is an actual hexadecimal display of the degrees Celsius. The microcontroller is used to start the ADC conversion and then monitor the

end of conversion (EOC) line to wait for the conversion to be complete. Once the conthe hexadecimal value into a BCD value so that it can be read by the user on the display of the DAC module. The analog output value of the DAC is not used. The ASM51 software used by this application is given in Table 18–6. This listing basically has five columns. The first lists the memory locations 0000–0062 that are programmed in the EPROM. The next shows the actual hex contents of the memory locations, starting with 802E and continuing down through 22. The third and fourth show the assembly language programming with labels starting with the ORG 0008H and ending with the RET statement. In the extreme right-hand column is the comments section for the program. As you read through the comments section you will see that three subroutines are used to call the three different operations that are going to take place. The first subroutine, ADC, is used to float the buses on port 3 and port 1 and then issue the start con-

version (SC) signal. The “wait” part of that subroutine is necessary to wait until EOC After the ADC routine is complete and the digital value is stored in register 0, that value in register 0 must be converted from hex to BCD. To do this, a counter

◆ Figure 18–14 Celsius thermometer.

; LINK AREA

; CONVERSION

0032 1159 ACALL DAC ; DISPLAY RESULT AND ; CONVERSION

;

; INTO R0

004B 22 RET

; CONVERT HEX TO BCD ; AND DISPLAY ON DAC ; MODULE

; R0=ADC HEX ; RESULT

005D D4 DA A ; DECIMAL ADJUST Acc IF

005E D8FB DJNZ R0,LOOP3 ; DECR R0 WHILE INCR AND ; R0=0

0060 F590 MOV P1,A ; MOV CORRECTED BCD TO

0062 22 RET ;

0000 END

accumulator will have in it the correct BCD value that was achieved by using the decimal adjust instruction (DA A). After the DAC displays the BCD result, a delay is used for approximately 4 seconds so that there will be a 4-second delay before the temperature is refreshed.

Temperature-Dependent PWM Speed Control This application is shown in Figure this application is to monitor the temperature and produce a pulse-width-modulated (PWM) square wave whose duty cycle is proportional to the temperature. This PWM square wave can be used to drive a DC motor. The effective DC value will increase as the duty cycle increases. Because the duty cycle increases with increasing temperature, the speed of the motor will also increase with increasing temperature. The ASM51 software used to drive this application is given in Table 18–7. Basically, this software has two subroutines that are called. The first one is the ADC subroutine. This subroutine starts the conversion, waits until the conversion is complete, and moves the ADC result into register 0. The next subroutine, the PWM, is used to produce the PWM square wave. To produce a PWM square wave, the output of the DAC will first be held LOW (0 V) for a delay multiple equivalent to 10 hexadecimal. Then the DAC will be sent HIGH, which in this case is one-half the full-scale output (80 hex). This HIGH is held for a delay multiple equivalent to the temperature value received from the ADC conversion. This way, as the ADC result increases with increasing temperature, the duty cycle of the PWM will increase, thus increasing the effective DC value sent to the motor.

Integrating Solar Radiometer The block diagram for the integrating solar radiometensity and produce a real-time display of the irradiation from the sunlight and then accumulate the irradiation, the same as taking the integral, and display the integrated output as an analog voltage and also on a hex display. To measure the irradiation, an ECG 3034 phototransistor is used. It produces 300 nA per microwatt per centimeter

squared. The current is changed to a voltage by the 330- � resistor. This analog voltgram. The integrated output of the ADC will be proportional to the amount of sunlight that struck the measured surface over a certain length of time. This length of time could be one hour, one day, one week, or whatever time is desired. The software used to execute this application is given in Table 18–8. The first subroutine is the ADC subroutine, which is used to convert the irradiation into a digital value. After the microcontroller has this digital value, the DAC routine performs the integration simply by accumulating the ADC result over each period of time. The DAC provides both the hexadecimal equivalent of the integrated irradiation as well as an analog output voltage that is proportional to the integrated irradiation.

◆ Figure 18–15 Temperature-dependent PWM speed control.

; LINK AREA

; 1st LOOP

0032 1138 LOOP: ACALL ADC ; PERFORM AN A-TO-D

0034 114C ACALL PWM ; DRIVE DC MOTOR WITH

; 256th TIME FOR ; STABILITY

; (PROVIDES POSITIVE EDGE)

; Acc

; REG 0

0049 AF40 MOV R7,40H ; RESET REG 7 to 64 DECIMAL

004B 22 ERET: RET

; ADC OUTPUT VALUE

0051 98 SUBB A,R0 ; SUBTRACT THE ADC

0052 F9 MOV R1,A ; R1 (DELAY VALUE) FOR

; OUTPUT FOR A HIGH

0058 A900 MOV R1,R0 ; USE TEMPERATURE AS ; FOR HIGH

005A 115D ACALL DELAY ; CALL DELAY TO HOLD

005C 22 RET ; RETURN

; DOWN TO ZERO

0061 D9FA DJNZ R1,DELAY ; R1=MULTIPLIER FROM

◆ Figure 18–16 Integrating solar radiometer.

; LINK AREA

; CONVERSION

0034 1158 ACALL DAC ; DISPLAY RESULT AND ; CONVERSION

; INTO R0

004A 22 RET

; INTEGRATE BY ACCUMU; LATING ADC RESULT

0058 8840 DAC: MOV 40H,R0 ; MOVE ADC RESULT TO

005A 53403F ANL 40H,#00111111B ; MASK OFF UNWANTED

005D 2540 ADD A,40H ; ACCUMULATE NEW ADC ; TOTAL

;

0000 END

This three-module method for data acquisition and control proves to be a very inexpensive and simple way to be able to input both analog and digital quantities and to output both digital and analog quantities. Having the hex displays connected to the input and output modules is an effective way of monitoring the real-time activity of the DAC and the ADC. The entire three-module data-acquisition setup is very portable in that it requires only a bipolar power supply to operate it. The software used to exercise these modules is very straightforward and is effectively written using the ASM51 assembler on a personal computer and downloaded to an EPROM using a standard EPROM programming software package. Once you have the programmed EPROM, all that is required for a stand-alone data acquisition system is a power supply.

Summary

In this chapter we have learned the following:

1. 1. The 8051 microcontroller is different from a microprocessor because it

has the CPU, ROM, RAM, timer/counter, and parallel and serial ports fabricated into a single IC.

1. 2. Thirty-two of the 40 pins of the 8051 are used for the four 8-bit parallel

I/O ports. Three of the ports share their function with the address, data, and control buses.

1. 3. The address spaces of the 8051 are divided into four distinct areas: in-

ternal data memory, external data memory, internal code memory, and external code memory. The internal data memory is further divided into user RAM and Special Function Registers (SFRs).

1. 4. To interface to an external EPROM like the 2732, an octal D-latch is

required to demultiplex the address/data bus, which is shared with port 0.

The External Access (EA) pin is tied LOW and the (PSEN) output is used

1. 5. Extra data memory and I/O ports can be interfaced by using the 8155

IC. The 8155 demultiplexes the address/data bus internally so an octal D-latch is not required.

1. 6. The MOV instruction is very powerful, providing the ability to move

data almost anywhere internal or external to the microcontroller and to the I/O ports.

7. Program branching is accomplished by use of many different condi-

tional and unconditional jumps and calls.

1. 8. The 8051 instruction set provides the ability to work with individual

bits, which makes it very efficient for on/off control operations. Instructions are available for all the logic functions, rotates, and bit manipulations.

1. 9. Instructions are provided for all the basic arithmetic instructions: addi-

tion, subtraction, multiplication, division, incrementing, and decrementing.

1. 10. Each instruction machine cycle takes 12 clock periods to complete.

This means that if a 12-MHz crystal is used, each machine cycle takes 1 s m

single I/O port.

1. 12. Interfacing an 8-bit analog-to-digital converter to an 8051 is accom-

plished with one port and two bits on a second port. The start-conversion LOW pulse is issued with bit-setting instructions and the end-of-conversion signal is monitored with bit-checking instructions.

Glossary

Assembler: A software package used to convert assembly language programs into executable machine code. Bidirectional: An I/O port that can be used for both input and output. Bit Addressable: Memory spaces in the internal RAM and SFR areas that allow for the addressing of individual bits.

External Access (EA): An active-LOW input that when forced LOW, tells the procesMicrocontroller: A computer on a chip. It contains a CPU, ROM, RAM, counter/ timers, and I/O ports. It is especially well suited for control applications.

Program Store Enable (PSEN): An active-Low output control signal issued by the Register Bank: A group of eight registers. The 8051 has four sets of banks that are selected by writing to the two bank-select bits in the PSW. Special Function Register (SFR): A data register that has a dedicated space within the microcontroller. It is used to maintain the data required for microcontroller operations.

Problems

18–1. Why is a microcontroller sometimes referred to as a “computer on a chip”? 18–2. Describe the difference between the 8031, 8051, and the 8751. 18–3. What additional features does the 8052 have over the 8051? 18–4. Port 2 has a dual purpose. One is as a bidirectional I/O port. What is its other purpose? 18–5. If you are using the internal ROM in the 8051 for your program code

memory, should the EA be tied HIGH or LOW? to the 8051? 18–7. What is the address range of the Special Function Registers (SFRs)? 18–8. What are the SFR addresses of the four I/O ports? 18–9. The 8051 has four register banks with eight registers in each bank. How does the CPU know which bank is currently in use?

ing the 2732 EPROM in Figure 18–5 but not when interfacing the 8155 RAM in Figure 18–6? 18–11. Determine the value of the accumulator after the execution of instruction A:, B:, C:, and D: MOV 40H,#88H MOV R0,#40H

18–12. Repeat Problem 18–11 for the following instructions:

MOV 50H,#33H MOV 40H,#22H MOV R0,#30H MOV 30H,50H MOV R1,#40H

18–13. Write the instructions to perform each of the following operations: (a) Output a C7H to port 3. (b) Load port 1 into register 7. (c) Load the accumulator with the number 55H. (d) Send the contents of RAM memory, whose address is in register 0, to the accumulator. (e) Output the contents of register 1 to port 0. 18–14. Write a program that continuously reads port 0 until the byte read equals A7H. At that time, turn on the output LEDs connected at port 1. 18–15. Write a program that will produce an output at port 1 that counts up from 20H to 90H repeatedly. 18–16. Determine the value of the accumulator after the execution of instruction A:, B:, and C: MOV A,#00H MOV R0,#36H

18–17. Repeat Problem 18–16 for the following program:

MOV A,#77H

18–18. Modify one instruction in Example 18–8 so that it will output eight pulses at port 0 instead of five.

outputs the result to port 1. 18–20. What is the length of time of the following time-delay subroutine? (Assume a 12-MHz crystal is being used.)

DELAY: MOV R1,#00H

LOOP: DJNZ R0,LOOP RET

Schematic Interpretation Problems

See Appendix G for the schematic diagrams. 18–21. Find Port 2 (P2.7–P2.0) of U8 in the 4096/4196 schematic. This

port outputs the high-order address bits for the system (A8-A15). On a sep-

A8-A11 to the four bits A12-A15. The HIGH output for an equal compari18–22. Locate the microcontroller in the 4096/4196 schematic. (a) What is its grid location and part number? (b) Its low-order address is multiplexed. What IC and control signal is

Appendix A Web Sites

Useful Web sites for this book include the following: www.acebus.com (AceBus) Downloadable 8051 microcontroller editor, assembler, and simulator www.ahinc.com/scsi.htm (Advanced Horizons, Inc.) SCSI, CD, and DVD definitions and standards www.allegromicro.com (Allegro MicroSystems, Inc.) Hall Effect Sensors and Power ICs www.altera.com (Altera Corporation) CPLDs and FPGAs www.ocf.berkeley.edu/~amanb/8085.html 8085 simulator www.amd.com (Advanced Micro Devices, Inc.) Microprocessors, EPROMs, and Flash memory www.analog.com (Analog Devices, Inc.) Analog ICs, ADCs, and DACs www.bipom.com (BiPom Electronics, Inc.) Downloadable 8051 microcontroller editor, assembler, and simulator www-03.ibm.com/chips/ (IBM Microelectronics Corporation) Microprocessors, SRAMs, DRAMs, and custom logic www.datasheetcatalog.com pdf datasheet downloads www.digikey.com Sales catalog of electronic products and components www.educypedia.be/electronics Free circuit schematics, information and tutorials www.elexp.com (Electronics Express, Inc.) Sales of electronic products, CPLD

programmer boards, and microprocessor trainers and components www.emacinc.com (EMAC, Inc.) Microprocessor and microcontroller trainers and single-board computers www.fairchildsemi.com (Fairchild Semiconductor, Inc.) Digital Logic ICs, analog ICs, discrete semiconductors, EEPROMs, and microcontrollers www.fujitsumicro.com (Fujitsu, Inc.) Microcontrollers, DRAMs, and Flash memory

memories, EEPROMs, digital logic ICs, analog ICs, and discrete semiconductors www.howstuffworks.com (HowStuffWorks) Beginners guide to the operation of electronic and computer hardware and software www.idt.com (Integrated Device Technology, Inc.) SRAMs and digital logic ICs www.intel.com (Intel Corporation) Microprocessors, microcontrollers, and Flash memory www.interactiv.com (Interactive Image Technology, Inc.) Multisim®software www.intersil.com (Intersil Corporation) Analog ICs, ADCs, DACs, SRAMs, microprocessors, microcontrollers, and discrete semiconductors www.jameco.com Sales catalog of electronic products and components www.jdr.com Sales catalog of electronic products and components www.latticesemi.com (Lattice Semiconductor Corporation) CPLDs www.linear-tech.com (Linear Technology Corporation) ADCs and DACs www.microchip.com (Microchip Technology, Inc.) EEPROMs and microcontrollers www.micronsemi.com (Micron Semiconductor Products, Inc.) DRAMs, SRAMs, and Flash memory www.mot-sps.com (Motorola Semiconductors, Inc.) Analog ICs, digital logic ICs, microcontrollers, microprocessors, SRAMs, and discrete semiconductors www.mp3-tech.org (MP3 Tech) MP3 definitions and standards www.national.com (National Semiconductor Corp.) Analog ICs, digital logic ICs, and microcontrollers

www.ni.com (National Instruments, Inc.) Provider of Multisim simulation software and LabView measurement and control software www.nxp.com (NXP Semiconductors N.V.) Digital and Mixed Signal logic ICs www.onsemi.com (ON Semiconductor, Inc.) Analog ICs, digital logic ICs, and discrete semiconductors www.pctechguide.com (PCTechGuide) Technicians guide to PC hardware and software www.semiconductors.philips.com (Philips Semiconductors, Inc.) Analog ICs, digital logic ICs, microcontrollers, and discrete semiconductors www.sharpmeg.com (Sharp Microelectronics Corporation) Microprocessors, microcontrollers, SRAMs, and Flash memory www.terasic.com Provider of Altera FPGA Development and Education boards like the DE-x series www.ti.com (Texas Instruments, Inc.) Analog ICs, digital logic ICs, and microcontrollers www.toshiba.com (Toshiba America, Inc.) Analog ICs, digital logic ICs, microcontrollers, DRAMs, SRAMs, and Flash memory www.usb.org (Universal Serial Bus) USB definitions and standards www.webopedia.com Glossary of PC and internet terms with links to other sites www.xess.com (XESS Corporation) CPLD programmer boards www.xilinx.com (Xilinx, Inc.) CPLDs and FPGAs www.zilog.com (Zilog Inc.) Microprocessors and microcontrollers

Appendix B Manufacturers’ Data Sheets*

Web Site Links to Complete Data Sheets and Useful

Reference Material

NXP Semiconductors [Formerly Philips (Signetics) Semiconductor]

74F00 NAND http://www.nxp.com/documents/data_sheet/

74F112 Flip-Flop http://www.nxp.com/documents/data_sheet/

74HC/HCT00 NAND http://ics.nxp.com/products/hc/datasheet/

74LV00 Low-V NAND http://www.nxp.com/documents/data_sheet/

74ABT244 Buffer http://www.nxp.com/documents/data_sheet/ *Courtesy of NXP Semiconductors, Fairchild Semiconductors, Xilinx, Inc., and Altera Corporation.

National Semiconductor

STmicroelectronics

27C64 EPROM http://www.st.com/stonline/books/pdf/docs/2388.pdf

Altera Corp.

EP2C Cyclone II FPGA http://www.altera.com/literature/hb/cyc2/

Atmel Corp.

8051 instruction set http://www.atmel.com/dyn/resources/

Mini-Circuits Inc

ESD Prevention http://www.minicircuits.com/appnote/an40005.pdf

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

(Used with permission from NXP Semiconductors.)

Device Family Data Sheet

This section provides information for board layout designers to successfully layout their boards for Cyclone®II devices. It contains the required PCB layout guidelines, device pin tables, and package specifications. This section includes the following chapters:

on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.

Altera Corporation Section I–1 (Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

CII51001-3.2

Introduction Following the immensely successful first-generation Cyclone® device

family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who compromise power consumption and performance for low-cost, Altera’s latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% higher performance and half the power consumption of competing 90-nm FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions. Reference designs, system diagrams, and IP, found at www.altera.com, are available to help you rapidly develop complete end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows you to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Single or multiple Nios II embedded processors can be designed into a Cyclone II device to provide additional co-processing power or even replace existing embedded processors in your system. Using Cyclone II and Nios II together allow for low-cost, high-performance embedded processing solutions, which allow you to extend your product's life cycle and improve time to market over standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve price-to-performance ratios for digital signal processing (DSP) applications. You can implement high-performance yet low-cost DSP systems with the following Cyclone II features and design support:

February 2008 (Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

design environment

I DSP Development Kit, Cyclone II Edition low-cost applications including a wide range of density, memory, embedded multiplier, and packaging options. Cyclone II devices support a wide range of common external memory interfaces and I/O protocols required in low-cost applications. Parameterizable IP cores from Altera and partners make using Cyclone II interfaces and protocols fast and easy.

Features The Cyclone II device family offers the following features:

logic

G 4,096 memory bits per block (4,608 bits per block including 512

G Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,

G True dual-port (one read and one write, two reads, or two

independent 9- × 9-bit multipliers with up to 250-MHz performance

RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL

G Single-ended I/O standard support, including 2.5-V and 1.8-V, and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL

G Peripheral Component Interconnect Special Interest Group (PCI operation at 33 or 66 MHz for 32- or 64-bit interfaces

G PCI Express with an external TI PHY and an Altera PCI Express

(Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use

G Three dedicated registers per I/O element (IOE): one input

settings

G MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and

configuration

division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control

G Up to 16 global clock lines in the global clock network that drive

100 ms

G Decompression feature allows for smaller programming file

G Supports multiple configuration modes: active serial, passive

G Supports configuration through low-cost serial configuration

G Device configuration supports multiple voltages (either 3.3, 2.5,

and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and

(Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

protocols. Visit the Altera IPMegaStore at www.altera.com to download IP MegaCore functions.

G Nios II Embedded Processor support offers a faster power-on-reset (POR) time. Devices that support the Fast-On feature are designated with an “A” in the device ordering code. For example, EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is only available in the automotive speed grade. The EP2C8A and EP2C20A are only available in the industrial speed grade. The EP2C15A is only available with the Fast-On feature and is available in both commercial and industrial grades. The Cyclone II “A” devices are identical in feature set and functionality to the non-A devices except for support of the faster POR time.

f Cyclone II A devices are offered in automotive speed grade. For more Handbook.

f For more information on POR time specifications for Cyclone II A and Cyclone II Device Handbook.

◆ Table 1–1 lists the Cyclone II device family features. Table 1–2 lists the

Cyclone II device package offerings and maximum user I/O pins.

(Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

◆ Table 1–1. Cyclone II FPGA Family Features (Part 2 of 2)

I/O pins Notes to Table 1–1:

(1) The EP2C15A is only available with the Fast On feature, which offers a faster POR time. This device is available in

(2) The EP2C5, EP2C8, and EP2C20 optionally support the Fast On feature, which is designated with an “A” in the devices are only available in industrial grade.

(3) This is the total number of 18 × 18 multipliers. For the total number of 9 × 9 multipliers per device, multiply the

(Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

(1) Cyclone II devices support vertical migration within the same package (for example, you can migrate between the

(2) The Quartus® II software I/O pin counts include four additional pins, TDI, TDO, TMS, and TCK, which are not

and DQS groups are supported. Vertical migration between the EP2C5 and the EP2C15 in the F256 package is not supported.

(6) The I/O pin counts for the EP2C5, EP2C8, and EP2C15A devices include 8 dedicated clock pins that can be used pins that can be used for data inputs.

(7) EP2C8A, EP2C15A, and EP2C20A have a Fast On feature that has a faster POR time. The EP2C15A is only available

(8) The EP2C5 optionally support the Fast On feature, which is designated with an “A” in the device ordering code. Device Handbook. Cyclone II devices support vertical migration within the same package (for example, you can migrate between the EP2C35, EPC50, and EP2C70 devices in the 672-pin FineLine BGA package). The exception to vertical migration support within the Cyclone II family is noted in Table 1–3.

(Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.)

Appendix C Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation)*

The IEEE/IEC standard for logic symbols introduces a method of determining the complete logical operation of a given device just by interpreting the notations on the symbol for the device. At the heart of the standard is dependency notation, which provides a means of denoting the relationship between inputs and outputs without actually showing all of the internal elements and interconnections involved. The information that follows briefly explains the standards publication IEEE Std. 91–1984 and is intended to help in the understanding of these new symbols. A complete explanation of the logic symbols is available from Texas Instruments, Inc., in Publication SDYZ001, “Overview of IEEE Std 91–1984.” They also have a publication (SZZZ003) entitled “Using Functional Logic Symbols,” which explains several applications of the symbols.

Explanation of Logic Symbols

F. A. Mann Texas Instruments Incorporated

Contents

1.0 INTRODUCTION 2.0 SYMBOL COMPOSITION 3.0 QUALIFYING SYMBOLS *Courtesy of Texas Instruments, Inc.

Institute of Electrical and Electronics Engineers, Inc. IEEE Standards Office 345 East 47th Street New York, N.Y. 10017 International Electrotechnical Commission (IEC) publications may be purchased from: American National Standards Institute, Inc. 1430 Broadway New York, N.Y. 10018

Appendix D Answers to Odd-Numbered Problems

Chapter 1 (d) Tanks B and C, temperature high

(e) Tank C, temperature and pressure high

1–1. (a) 610 (b) 1110 (c) 910 (d) 710

1–19. (a) sku43 (b) 534B55343316

(e) 1210 (f) 7510 (g) 5510 (h) 18110

(e) 1558

Chapter 2

1–5. (a) 2310 (b) 3110 (c) 1210 (d) 5810

(e) 8110

Vout2

Vout

(c) Tanks B and D, pressure high 0 V

(IC = 5V>RC)

2–17. The totem-pole output replaces RC with a

(c) X = A + B + C

The transistor prevents excessive collector 3–7. A high-level output when turned on.

2–19. (a) 8.0 MHz (b) 125 ns B

2–21. P3 parallel, P2 serial

X 2–23. A HIGH on pin 2 will turn Q1 on, making RESET_B approximately zero.

E2–1. (a) Let (b) 24 A

Cp = 5V>0V,Vout3 = 0V>5V,

E2–3. (a)

B

(c) Cp and Vout3 are in phase.

E2–5. (a) V1 = 4.3V,V2 = 0V,V3 = 4.3V,

3–9.

3–11.

(b) A B C D X

3–17. Two

3–39. U = Cp,A,B W = B,C

3–19. To provide pulses to a digital circuit for

X = 1 3–43. HIGH; to see inverted output pulses

Y = 1 (otherwise, output would always be HIGH). 3–45. There is no problem.

3–31. W = 1

3–47. With all inputs HIGH, pin 8 should be

X = 0 LOW. Next try making each of the 8 inputs Y = 0 LOW, one at a time, while checking for a Z = 0 HIGH at pin 8.

location B7

A = LOW (GND), pin 40 HIGH (+5)

B 3–53. Place probe-A on the input of the inverter

C (WATCHDOG_CLK). Using the same of U4:A. Probe-B should display the

X complement of probe-A.

E3–1. (a) X = 1,Y = 1

D (b) X = 0,Y = 0

(c) A B X A B Y

Y

1 1 1 1 1 1

E3–5. (a) Vcc (b) Logic pulser (c) Logic probe

(d) Ground (e) Vcc C

E3–7. (a) X = 0,Y = 0

Chapter 5

E3–11. (a) NAND (b) NOR

E3–13. (a) X = C¿,D¿,Cp (b) Y = BD¿ 5–1. W = (A + B)(C + D)

X = AB + BC E3–15. (a) U1b, U1c, U1d are bad. Y = (AB + B)C (b) U2a, U2c are bad. Z = (AB + B + (B + C))D E3–17. (a) U1b, U1c are bad.

5–3. (a) A

(b) U2a, U2d are bad. B M

Chapter 4 C

D

4–1. The 7400-series uses hard-wired logic. The (b) A

N D contains thousands of logic gates that can (c)

C

4–5. (a) 3 (b) 5

(d) A B

4–9. The PLA provides programmable OR gates

for combining the product terms. B

4–11. So it will not lose its programmed logic C

4–13. The look-up table method

4–15. They must be reprogrammed. B

4–17. It translates the information from the C

S design entry stage into a binary file that is D later used to program the CPLD. 4–19. Text

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 1 0 0 1 1 0 0 1 0

0 0 1 0 1 0 0 0 0 0 1 0 0

A

C

1 0 1 0 1 0 0 0 1

(c) Distributive law B

5–7. Z

C Z = ABC + CD

X

B 5–13. Break the long bar and change the AND to

an OR, or the OR to an AND.

Y = A + BC 5–17. C B A

Z = AB + B + BC A NC A W W = A+B

A B

5–9. B

X X = B+C Y

D B D V C A

C C 5–19. W

B (b)

D X = A C

Y 5–33. (a)

5–35. u. SOP x. SOP

5–23. A v. POS y. POS

Z = AC + AB + ABC

5–25. (23) A

1 0 0 1 1 1

5–47. (a)

1 1 1 1 1 0

5–29. (c) quad 2 input AND

(a)

E5–1. (a)

(c) (b) B = D(K + H) (d) (b) X = BC + A

(b) Y = AB + AB �AB = 1

(c) B 6–9. A7 = 101001110

FF = 111111111 E5–11. (a) 6

(b) Gate 2

(c) 6–13.

A TRANSMISSION

B 6–15. Yes; LOW

A8 A12 6–5. X1

A10 A14 Ex-OR X3 A11

B A15

7–15. b, c, e

7–19. Co = NO

E6–3. (a) Yes, because it is an Ex-OR. 7–21.

Chapter 7

(h) 111 1110 1000 0001

Also, the full-adder fourth from right is

7–9. (a) 0000 1100 (b) 0000 0110

bad.

+5 A7•• A0 A4 77 2D FF 1D

order A = B

(b) Full adder TT A > B The number of HIGH inputs is two or

(b) See lower numbers.

8–7. Active LOW outputs are 0 when selected.

8–3. (a)

t5-t6 2

(b) 0, 1, 0, 1, 1 EI 8–29. (a) The 74150 is not working. The data select is set for input D7, which is 0. I3

for input I0, which is 1. Y should equal

1 and Y should equal 0, which they do. (c) The 74139 has two bad decoders.

A1 Decoder A is enabled and should outA2 disabled and should output 1111 but EO does not. (d) The 74154 is OK. The chip is disabled,

GS so all outputs should be HIGH, which 8–17. 8–31. (a) Write to memory bank 5, location 3H.

C7H.

1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

(d) 10001002

8–41. 74151

8–21. See #20 (lower numbers). 4 I0 Z 5

TC

To E1 To E2

E8–1. (a) A0 to A3 = B0 to B3

To E3 (b) NOR

Y0 Y1

Y2 Data out

9–11. 7400:PD = 75mW(max)

E8–9. (a) 00 (b) 11 74LS00:PD = 15mW(max)

E8–13. (a) LED2

9–19. Because MOS ICs are prone to electro-

static burnout.

Chapter 9

9–21. Where speed is most important, ECL is

100 nS G D

10–11.

E9–1. (a) HIGH (b) ON, OFF (c) OFF, ON

E

E9–3. (a) 12 ns, 12 ns (b) 6.3 ns, 11 ns

C9–1. (a) 4 mA to 24 mA (b) 2 mA to 8 mA

D C9–3. (a) 1.7 V, 0.7 V, 2.0 V, 0.4 V

(b) 1.17 V, 0.630 V, 1.35 V, 0.45 V Q

Chapter 10

10–15.

10–17. The 7474 is edge-triggered; the 7475 is

pulse-triggered. The 7474 has asynchro-

triggered device as opposed to being pulsetriggered. S 10–21. R

1 VCC 14 +5 V CP

10–5. D

Q G Q

10–7. G D

10–23. The toggle mode

Q 10–25. The 7476 accepts J and K data during the entire positive level of CP, whereas the 74LS76 only looks at J and K at the negaQ tive edge of CP.

7 GND 8 7 GND 8

RD Sd′

J Rd′ Q Q1

E10–7. (a) J = 0,K = 1, pulse Cp¿ LOW then

Q2 HIGH

(e) Set: Pulse S LOW then HIGH; Reset:

SD Pulse R LOW then HIGH Data

Q Cp′

10–31. K

CP Sd′ Q SD Q

Chapter 11

10–33. The ¿373 is a transparent latch. If the tim- 11–1. RD will pass through to Q while E is HIGH Cp and latch on to the data when E goes LOW.

Q

flicker. The ¿273 is the preferred device,

11–3. ta = 20ns td = 30ns

10–35. (a) HIGH (b) no (c) Qa must go tb = 30ns te = 20ns

HIGH while WATCHDOG_EN is HIGH. tc = 20ns tf = 30ns 11–5. Proper circuit operation depends on tp of HIGH.)

the 7432 being �10ns. The worst-case tp is specified as 15 ns, but the actual tp may

E10–1. (a) 1, 0 be less. If it’s actually less than 10 ns, the

(b) 0, 1 circuit won’t operate properly. E10–3. (a) Top inverter (b) Vcc (c) None (d) R switch

Rlim RD

J, K Q2 25 ns

Q5

11–9. Q6

Q7

3.6 V Q8 0.2 V

0.7 V 1.9 V 11–25. The switches of U12 and the pull-up resis-

Vin tors are used to place either a HIGH or place a HIGH on one of these lines, the

11–11. corresponding switch must be open. A

closed switch pulls the line to ground. 2.4 V

E11–1. Vt += 1.6V, Vt -= 1.3V

1.7 V

Vin 0.9 V 0.4 V 3.4 V 0V

Vout 1.3V 1.6V

E11–3. (a) Vt += 1.3V, Vt -= 0.83V

tHI = 1.8 volts change Voh = 5V,Vol = 0V tLOW = 2.2 volts change DC = 45% +5V 11–13. It is caused by switch bounce. If the switch

bounces an even number of times, the LED 0V will be off. A debounce circuit would

Check the fuse. If the fuse is OK, you should check for approximately 12.6 V ac

at the transformer secondary and 20 V dc Chapter 12

+ >-

at the output of the diode bridge and the input to the 7805. sequence of digital states triggered by a

11–17. Light: VA = 0.0495V

timing pulse or clock. Combination logic

Dark: VA = 4.55V

11–21. Icoil = 240mA

RD Cp0

1 K RD 1 K RD 1 K RD D Q 12–19. Q

1 20 1 21 1 22 1 23

12–21. Q

12–13. (a) 2 (b) 4 (c) 4 (d) 5 12–23. +5 V to RD

12–25. Yes, it will work. The inputs to the AND

22 are normally 1–1 until the push button is If either AND input goes LOW, its output goes LOW, resetting the counter. This is

12–27. PL

Output TCU

Q1

12–29. Q2

Input

ppm) (60 pph)

PL an 1110 when

PL D0 D1 D2 D3

12–31. CpU CpU TCU

74193

100 Hz

12–37. 12–43. (a) HIGH-order U10, LOW-order U9

CP 12–45.

E

E12–3. Doesn’t count past 7. Bad MS flip-flop

it with a NAND gate that outputs a

Cp 0 1 2 3 4 5 6 7 8 9 MR E12–9. S0 S1 MR PL Q0 Cpu

Cpd Q1 Qa

Qc L

Qd D 13–21. Tcu'

L D 13–13.

Cp 0 1 2 3 4 5 6

MSB LSB allows data to flow in only one direction; a 13–25. The 74164 is a serial-in, parallel-out, transceiver is bidirectional. whereas the 74165 is a serial- or parallel-

the CLK input of U30. When pin 3 of

Serial in U13:A is LOW, a HIGH will appear at LE of U33. This allows the valid data at D0–D7

which causes the data outputs of U33 to re-

also enables the decoder U23. Just before

1 1

Serial out OE 1–0–1 to provide an active output at /IOADDR. This is the clock input for U30,

U32, the same process is followed, except

OE

E13–1. (a) 3 (b) R, S, C, S, C, S, C, S

SERIAL FLOAT 1 0 1 1 0 1 0 0 (b) Q^0 Q^1 Q^2 Q^3

VCC

Chapter 14 Rx 12.9 kΩ

Cx = 0.047 μF

14–1. (a) Monostable (b) Bistable

(c) Astable Output

14–3. 75.6ms NPRO

T

14–5. 32.6ms 1

14–7. Because a Schmitt device has two distinct 1

charges and discharges between those two

VC

2.0 V B

6 V Q1 Q2

0 V tw1 = 0.20 μs tHI = 126 μs tLO = 160 μs

DC = 44.1% f = 3.5 kHz 14–17. @0�,f = 89.0kHz

DC = 71.0%

14–11. @10k�,f = 39.8kHz

DC = 59.4%

VCC VCC

C Vout T .01 μF Vin 74121 Pick Cx = 0.001 μF; Rx = 7.21 kΩ

14–23. Chapter 15

VCC 15–1. Converts physical quantities into electrical quantities

8.5K 15–3. Very high input impedance, very high volt-

74LS123

15 RCext age gain, and very low output impedance

Ttrigger:Ttot = 1>10kHz = 100

E14–3. mS, 0 1 0 1 -6.25

15–9. All values of Vout would become positive.

15–35. 9.60 kg

15–37.

0 1 1 1 -1.75 1 1 1 1 -3.75

Vout would be 0 to 7.47 V.

15–19. P2.0

VCC

150 pf

Analog input

voltage (in volts) D2 = -4V,D3 = -8V (c) D3, D2, (D2 and D1), (D3 and D1 and

15–21. (a) 0 V (b) They are equal. D0)

(d) 16

15–23. ttot = 8 * 50kHz= 0.16ms (e) 6.25k�

E15–3. (a) Output

15–25. %error = -0.197%

LOW

(d) 1.0 V

multiplexer select inputs. The voltage level passes to the LF 198, which takes a sample at some precise time and holds the level on the hold capacitor. The LH0084 adjusts the voltage to an appropriate level to pass into the ADC. The microprocessor issues

(c) 60 ns max 16–1. Bipolar, faster; MOS, more dense. 16–19. Address line multiplexing and memory

16–3. Data are being written into memory from refresh cycling

the data bus. Bus contention occurs only 16–21. 2864 when two or more devices are writing to 16–23. the data bus at the same time. 16–5.

B000 - BFFF

1 E3 2 ADDR 010

E

16–27. The circuit design will be similar except

16–7. CS = LOW,WE = LOW

the 2716 address inputs are A0 to A10. The

16–9. 10, 12, 13 new 74LS138 connections will be as

16–11. (a) 8192 (b) 16,384 (c) 65,536 follows:

(d) 16,384

or more.

A11 A0

16–17. (a)

16–29. Read cycle:

Din Valid data in

16–33. (a) Hard disk (b) DVD (LDA); (2) and (3) Pulse: read address

32k * 8 bytes at 2001, 2002 (4000H); (4) Pulse: read data at address 4000H

16–37. (a) 8k * 8 (b) SMN_SEL, MON_SEL

17–17. A high-level language (FORTRAN, BASIC,

(c) A000H–BFFFH (d) E000H–FFFFH

(b) Outputs are all stuck LOW. 17–19. (a) LOW (b) LOW

Chapter 17 (c) HIGH

(d) HIGH 17–1. A microprocessor-based system would be 17–21. U6a and U6b are drawn as inverted-input used whenever calculations are to be made, NAND gates to make the logical flow of decisions based on inputs are to be made, a the schematic easier to understand. memory of events is needed, or a modifi-

17–23. (a) IN instruction, RD is pulsed LOW.

(b) OUT instruction, WR is pulsed LOW.

17–25. (1) A8toA15 = FEH

lar location or device within the system.

(2) IO/M = HIGH

(3) WR is pulsed LOW/HIGH 74LS244

17–29. 2010 3E

17–7. The input port has three-stated outputs so

17–9. 216(65,536)

E17–1. (a) LOW

17–11. It stores the contents of the accumulator (b) Press C

(c) Put 7C on the switches, make OE¿ = 0 (data appear on the data bus), press C 17–13. Instruction decoder and register: register

[data appear at output port if OE¿ (G) is LOW]. receives the machine language code and produces the internal control signals re-

quired to execute the instruction. Chapter 18

18–1. Because it has RAM, ROM, I/O Ports, and

a Timer/Counter on it 18–3. Extra 4 K ROM, 128 bytes RAM, 16 bit Timer/Counter, 1 interrupt

18–7. 80H-FFH ADD A,#05H

MOV P1,A 18–9. By reading the two bank-select bits

A8

18–13. (a) MOV P3,#0C7H (b) MOV R7,P1 A12

(c) MOV A,#55H (d) MOV A,@R0

18–15. START: MOV A,#20H

LOOP: MOV P1,A X2 P3.4

INC A A14 X3

X4 (c) A = EBH

Appendix E VHDL Language Reference

Library-Entity-Architecture Model

Figure E–1 is a sample VHDL program showing the syntax rules and language format of a basic program.

Figure E–1 VHDL program model showing the syntax for Library, Entity, and Architecture

Program, Entity, and Architecture Naming Conventions

Valid VHDL names can consist of letters, numbers, and the underscore (_) character [hyphens (-) are not allowed]. The name must start with a letter and cannot contain spaces.

Valid Names Invalid Names

Comments can be placed within a VHDL program to document a particular statement or group of statements. Any words preceded by a double hyphen (--) are considered to be a comment for documentation purposes and will be ignored by the VHDL compiler.

Sample Comments

-- Boolean solution to example 5-3 -- Problem C5-3 --

General VHDL Rules

VHDL logical operators have no order of precedence so the order must be explicitly

defined using parentheses. For example, the Boolean equation x = a + bc must be sult of the operation on the right-hand side to the left-hand side.) Also note that VHDL is not case-sensitive so the letters a, b, and c could have been capitalized, but the convention used by most VHDL programmers is to only capitalize the reserved keywords like AND, OR, PORT, ENTITY, and so on. (See Figure E–1.)

Logical Operators

The logic operators are used to perform Boolean bit-wise operations on individual bits or arrays of bits. (Example: x 6= a AND b;)

Operator Description

Relational Operators

The relational operators are used to test the relative values of two scalar types. The result is a Boolean true or false value. [Example: IF a * b THEN result *�"001". This is interpreted as “if the logic (a less than b) is true, then the bit string "001" is moved to the variable result.”]

Operator Description

The arithmetic operators are used to perform mathematical operations. (Example: sum_ string6=astring+bstring+cin;) The following is a partial list of the arithmetic operators.

Operator Description

> Division

Data Types

The data type defines the type of value that can be used with the specified input, output, or internal signal. The most common data types used are as follows:

Type Values

std_logic Data Type Values

The values that the std_logic data type can have are defined as follows:

Value Description

fig5_62.vhd A vector with 3 elements Selected signal assignment for i = 3, 2, 1 then 0 ex6_10.vhd Loop 4 times

input (0) input (1) input (2) (c,d)

◆ Figure 6–24

Declare which VHDL Entity name

parentheses are required for Define the logic

Architecture name ex5_17.vhd

3-bit internal SIGNAL result

Assign vector elements compare_8b.vhd a2

y0 y7 Sensitivity list

◆ Figure 8–19

◆ Figure 8–5

4-bit output Asynchronous Reset has priority Negative clock edge

Input and output mod16up.vhd Defines a new the allowable

Assign binary to q state_gray.vhd

to next state. based on value

Input to equation of state.

Appendix F Review of Basic Electricity Principles

Definitions for Figure F–1

through a pipe R

+ I –

Figure F–1 Series circuit used to illustrate Ohm’s law.

Common Engineering Prefixes

Prefix Abbreviation Value

The current (I) in a complete circuit is proportional to the applied voltage (V) and inversely proportional to the resistance (R) of the circuit (see Figure F–2). Formulas I =V R V = I * R R =V I V

EXAMPLE F–1

(a) Determine the current (I) in the circuit of Figure F–1 if V = 10V and

(b) Recalculate the current if R = 4�.

doubled to 4� in (b). R = 10�. (e) What voltage would be required in (d) if you only need one-half that current?

(f) If V = 12V in Figure F–1, what resistance is required to limit the cur(g) To limit the current to 1 A in (f), what resistance would you need?

Solution:

(c) As the resistance to current flow doubled, the current dropped to one-half.

resistance.

Apply the values listed below to the circuit of Figure F–1 to determine the unknown quantity.

Solution:

24 * 10-6A

EXAMPLE F–3

A series circuit has two or more resistors end to end. The total resistance is

equal to the sum of the individual resistances (RT = R1 + R2). Also, the

I

Solution:

RT = 8k�+ 2k�= 10k� 10V

I = 10k�= 1mA VR2 = 1mA * 2k�= 2V

Notice that the voltage across any resistor in the series circuit is proportional to the size of the resistor. That fact is used in developing the voltage- divider equation: R2 VR2 = VS * R1 + R2 2k� = 10V * 2k�+ 8k� = 2V

EXAMPLE F–4

Use the voltage-divider equation to find Vout in Figure F–4. (Vout is the voltage from the point labeled Vout to the ground symbol.)

Vout

to ground. Solution: 2k� Vout = 12V * 2k�+ 4k� = 4V

EXAMPLE F–5

A short circuit occurs when an electrical conductor is purposely or inadvertently placed across a circuit component. The short causes the current to bypass the shorted component. Calculate Vout in Figure F–5. 4 kΩ Vout

12 V 2 kΩ Short Ground (V = 0)

EXAMPLE F–7

An open circuit is a break in a circuit. This can be done purposely by an electronic switching component, or it could be a circuit fault caused by a bad connector or burnt-out component. This break will cause the current to stop flowing to all components fed from that point. Calculate Vout in Figure F–7. Open 4 kΩ I =0A 12 V Vout 2 kΩ

V2k�= 0A * 2k�= 0V Vout = V2k�= 0V

Calculate Vout in Figure F–8.

I =0A 4 kΩ 12 V 2 kΩ Open

Figure F–8 An open circuit below the measurement point allows the entire

Solution: Because I = 0A,

Vdrop(4k�) = 0A * 4k�= 0V Vout = 12V - Vdrop = 12V

Note:

This is probably the hardest concept to understand. Another way to explain why the entire supply reaches Vout is to assume that an open circuit can be

open, the calculation will be 10,002,000

Vout = 12V * 10,002,000 + 4,000= 11.995V The symbol for a battery is seldom drawn in schematic diagrams. Figure F–9 is an alternative schematic for a series circuit. Solve for Vout. +12 V 4 kΩ Vout 2 kΩ

Figure F–9 Series circuit drawn without the battery symbol. 2k� Vout = 12V * 2k�+ 4k� = 4V

A relay’s contacts or a transistor’s collector–emitter can be used to create opens and shorts. Figure F–10(a) uses a relay to short one resistor in a series circuit (relay operation is described in Section 2–6). Sketch the waveform at Vout in Figure F–10(a). +12 V 4 kΩ Vout

0 V (a) 5 V Cp 0 V

4 V Vout 0 V (b)

Figure F–10 Using a relay to intermittently short the 2@k� resistor.

2@k� resistor and making Vout = 0V. When the coil is deenergized, the 2k� Vout = 12V * 2k�+ 4k� = 4V The clock oscillator (Cp) and Vout waveforms are given in Figure F–10(b).

Review Questions

F–1. What value of voltage will cause 6 mA to flow in Figure F–1 if

R = 2k� (3 V, 0.333 V, or 12 V)? _________ (increased/decreased). F–3. In a series voltage-divider circuit like Figure F–3, the larger resistor will have the larger voltage across it. True or false?

VR2 will be close to __________ (0 V/10 V). _________ (6 V/12 V). F–6. A short circuit causes current to stop flowing in the part of the circuit not being shorted. True or false? F–7. The current leaving the battery in Figure F–5 _________ (increases, decreases) if the short circuit is removed. F–8. The short circuit in Figure F–6 causes Vout to become 12 V because

(increase/decrease/remain the same)?

Answers to Review Questions

F–1. 12 V F–6. False

F–2. Decreased F–7. Decreases

F–3. True F–8. False

F–4. 0 V F–9. True

F–5. 6 V F–10. Remain the same

Problems

F–1. Refer to Figure F–1 to solve for the unknown quantities in the fol-

lowing table. [Example: For part (A), calculate the resistance if V = 12V

F–2. Repeat problem 1 for the following table.

lowing table.

F–4. Refer to the original Figure F–4 to solve for Vout given the following open- and short-circuit conditions. Vout

Answers to Problems

F–1(a). 3� F–3(a). 6 V

F–1(b). 4� F–3(b). 12 V

F–1(c). 5 A F–3(c). 6 V

F–1(d). 3 A F–3(d). 5.94 V

F–1(e). 12 V

F–1(f). 2.5 V F–4(a). 12 V

F–4(b). 0 V

F–2(a). 4k� F–4(c). 0 V

3k� F–4(d). 12 V

F–2(b).

F–2(c). 5mA

F–2(d). 4mA

F–2(e). 18 V

F–2(f). 2.5 mV

Appendix G Schematic Diagrams for Chapter-End Problems

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

(This item omitted from WebBook edition)

Appendix H 8051 Instruction Set Summary*

*Courtesy of Intel Corporation.

Index