MOS Device Physics — A Deeper Look

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

This chapter goes under the hood of the MOS transistor. We will not just state equations. We will explain why each part exists. We will use plain words and fresh numbers. By the end, you will understand drive strength, leakage, and the "second-order" effects that interviewers love to probe.

The Current Equation in Plain Terms

A MOS transistor is a switch with a dimmer. The gate voltage sets how much current flows from drain to source. We call this current the drain current, or I_D. First, a key term. The threshold voltage (V_t) is the gate voltage where the transistor "turns on." Below V_t, almost no current flows. Above V_t, current starts to flow. The "overdrive" voltage is how far past the threshold we push the gate. We write it as (V_gs − V_t). Here V_gs is the gate-to-source voltage. More overdrive means a stronger channel. A stronger channel means more current. The transistor has two main operating regions. The region depends on the drain-to-source voltage, V_ds.

THE TRIODE REGION

The triode region is also called the linear region. It happens when V_ds is small, specifically when V_ds < (V_gs − V_t). Here the transistor acts like a resistor. The current grows as you raise V_ds. The plain-language equation is: I_D = k' × (W/L) × [(V_gs − V_t) × V_ds − V_ds² / 2] Think of the channel as a hose. In triode, the hose is open along its whole length. More pressure (V_ds) pushes more water.

THE SATURATION REGION

The saturation region happens when V_ds is large, specifically when V_ds ≥ (V_gs − V_t). Here the current "flattens out." Raising V_ds barely changes the current. The simplified equation is: I_D = (k' / 2) × (W/L) × (V_gs − V_t)² In our hose analogy, the far end of the channel "pinches off." Adding more pressure does not add more flow. This is why the curve goes flat.

WHAT EACH VARIABLE MEANS

The term k' equals mobility times oxide capacitance (μ × C_ox). Mobility (μ) measures how fast carriers move under a field. Oxide capacitance (C_ox) measures how strongly the gate grips the channel. A thinner oxide gives higher C_ox and stronger control.

Why Current Depends on Overdrive and on W/L

Two factors set the basic drive strength. The first is overdrive. The second is the width-to-length ratio.

THE SQUARE-LAW DEPENDENCE ON OVERDRIVE

In saturation, current grows with the square of overdrive. So doubling the overdrive does not double the current. It quadruples it. Why squared? There are two reasons stacked together. First, more overdrive pulls more charge into the channel. That charge grows linearly with overdrive. Second, more overdrive also speeds up that charge. So we multiply charge by speed. Two linear effects multiplied give a square. This square-law is the classic "long-channel" model. Short transistors break it, as we will see later.

THE LINEAR DEPENDENCE ON W/L

Current grows linearly with W/L. Make the channel twice as wide, and you double the current. Make it twice as long, and you halve the current. Think of many parallel lanes on a highway. A wider transistor is like more lanes. More lanes carry more cars at once. A longer channel is like a longer, slower road. Cars take longer to cross, so flow drops.

DRIVE STRENGTH INTUITION WITH NUMBERS

Drive strength tells you how fast a gate can charge or discharge a load. Higher current means faster switching. Designers tune W to set drive strength. They rarely change L, because the process fixes the minimum L.

Worked Example 1: Relative Drive for Two W/L Ratios

Suppose two NMOS transistors share the same process and same overdrive. Both are in saturation.

• Transistor A: W = 4, L = 1, so W/L = 4
• Transistor B: W = 10, L = 2, so W/L = 5 Current scales with W/L. So the ratio of currents is: I_B / I_A = 5 / 4 = 1.25 Transistor B carries 25% more current. Notice that B is wider but also longer. The longer channel cancels some of the width gain. Only the ratio matters, not the raw width.

Worked Example 2: The Effect of Overdrive

Take one NMOS in saturation. Let k' × (W/L) = 200 µA/V². The factor of one-half is included separately. Use the saturation equation: I_D = (k'/2) × (W/L) × (V_gs − V_t)² So I_D = 100 µA/V² × (overdrive)². Case 1: overdrive = 0.4 V I_D = 100 × (0.4)² = 100 × 0.16 = 16 µA Case 2: overdrive = 0.8 V I_D = 100 × (0.8)² = 100 × 0.64 = 64 µA We doubled the overdrive. The current rose by 4×, from 16 µA to 64 µA. This shows the square-law in action. Small overdrive changes give large current changes.

Second-Order Effects, Explained Plainly

The simple equations above are a starting point. Real transistors deviate. These deviations are the "second-order effects." Interviewers expect you to name and explain each one.

CHANNEL-LENGTH MODULATION

In saturation, current should be flat versus V_ds. In reality, it rises slightly. Higher V_ds shortens the effective channel a tiny bit. A shorter channel carries more current. We model this with a factor (1 + λ × V_ds). Here lambda (λ) is the channel-length modulation parameter. It acts like a finite output resistance. This matters a lot for analog gain.

VELOCITY SATURATION

Carriers cannot speed up forever. At high electric fields, their speed hits a ceiling. We call this velocity saturation. This breaks the square-law. In short channels, the field is high even at modest voltage. So current grows closer to linearly with overdrive, not as a square. Short transistors are weaker than the ideal model predicts.

BODY EFFECT

The body (or substrate) is the silicon under the channel. Normally the source and body sit at the same voltage. If the source rises above the body, V_t increases. This is the body effect. It is also called the back-gate effect. It matters in stacked transistors, like in a NAND gate. The upper transistor sees a raised source. Its V_t goes up. That makes it slower.

DIBL (DRAIN-INDUCED BARRIER LOWERING)

DIBL means the drain voltage lowers the threshold. In short channels, the drain field reaches near the source. It helps pull carriers over the barrier. So a high V_ds lowers V_t. Lower V_t means more current and more leakage. DIBL is a short-channel headache. It makes the off-state current depend on drain voltage.

SUBTHRESHOLD CONDUCTION AND THE SUBTHRESHOLD SLOPE

Below V_t, the transistor is not fully off. A small current still leaks. This is subthreshold conduction.

This current does not follow the square-law. It follows an exponential law. Drop the gate voltage a little, and current drops by a fixed ratio. The subthreshold slope (often written S) measures this. It is the gate voltage needed to cut current by 10×. At room temperature, the best S is about 60 mV per decade. Real devices are worse, often 70 to 100 mV/decade. A smaller S is better. It means the transistor turns off sharply. A large S means lots of leakage near the threshold.

Why Leakage Rises as V_t Drops

We want fast transistors. Lower V_t gives more overdrive at a fixed supply. More overdrive means more speed. So why not just lower V_t to zero? The answer is leakage. Subthreshold current depends exponentially on V_t. Lower V_t means the device is "less off." Leakage rises fast as V_t falls. This is the core speed-versus-leakage tradeoff. Modern chips use multiple V_t flavors. High-V_t cells leak little but switch slowly. Low-V_t cells switch fast but leak a lot. Designers mix them by need.

TEMPERATURE EFFECTS ON MOBILITY AND V_T

Temperature changes two things at once. First, mobility (μ) drops as temperature rises. Hot silicon scatters carriers more. So drive current falls when the chip heats up. Second, V_t drops as temperature rises. Lower V_t would normally help current. But the mobility drop usually wins for on-current. So hotter chips are slower overall. For leakage, both effects make it worse. Lower V_t and higher temperature both boost subthreshold current. Leakage can rise sharply with heat. This can cause thermal runaway if not managed.

Worked Example 3: Subthreshold Current Ratio for a V_t Change

Subthreshold current changes by 10× for every S volts of gate change. Lowering V_t acts like raising the effective gate drive in the off state. Assume a subthreshold slope of S = 80 mV/decade. Suppose we lower V_t by 160 mV. Number of decades of change = 160 mV / 80 mV = 2 decades. Each decade is a 10× factor. Two decades give 10² = 100×. So lowering V_t by 160 mV raises the leakage current by 100×. This is a huge jump for a small voltage change. It shows why V_t selection is so careful. Let us add real numbers. Say the high-V_t cell leaks 1 nA per transistor. The low-V_t version then leaks 100 nA each. Across a million such transistors, that is 0.1 A of leakage difference. That alone can dominate the static power budget.

Gate Capacitance Components in Plain Terms

The gate is one plate of a capacitor. The channel and oxide form the rest. This capacitance must be charged and discharged when switching. It sets a big part of the delay and dynamic power. Gate capacitance has two main parts.

CHANNEL (INTRINSIC) CAPACITANCE

This is the capacitance from the gate to the channel through the oxide. It is the main, useful part. Its value is roughly C_ox × W × L. How this capacitance splits between source and drain depends on the region. In saturation, most of it leans toward the source. In triode, it splits more evenly. This split matters for accurate timing.

OVERLAP (PARASITIC) CAPACITANCE

The gate slightly overlaps the source and drain regions. This overlap is unavoidable in manufacturing. It creates a small fixed capacitance at each end.

Overlap capacitance does not depend on the operating region. It is always there. We model it as a constant per unit width. It becomes relatively larger as transistors shrink.

The total input capacitance a designer "sees" is the sum of both. There is also a gate-to-drain overlap that gets amplified during switching. We call that the Miller effect. It makes the gate-to-drain cap look larger than its raw value.

Interview Q&A

Overdrive affects current twice. It sets how much charge fills the channel. It also sets how fast that charge moves. Two linear effects multiply into a square. W/L only sets the channel's size, a single geometric factor. So it stays linear.

Carriers hit a maximum speed in high fields. Short channels have high fields even at low voltage. So current stops growing as a square of overdrive. It grows closer to linearly instead. Short devices give less current than the ideal model predicts.

The body effect raises V_t when the source sits above the body voltage. It bites in stacked transistors. In a NAND gate, the top transistor has a raised source. Its V_t rises, and it conducts less. This slows the gate and complicates timing.

Subthreshold current depends exponentially on V_t. A small V_t drop shifts the whole exponential curve up. With an 80 mV/decade slope, lowering V_t by 80 mV raises leakage 10×. The relationship is exponential, not linear, so it compounds fast.

DIBL is drain-induced barrier lowering. The drain voltage lowers the effective threshold. In short channels, the drain field reaches near the source. It helps carriers cross the barrier. So V_t falls at high V_ds, raising leakage. Long channels keep the drain too far away to matter.

It gets slower. Two things happen with heat. Mobility falls, which cuts on-current. V_t falls, which would help slightly. The mobility loss usually wins, so on-current drops. Worse, leakage climbs sharply, raising static power and heat further.

Key Takeaways

• The drain current has two regions. Triode acts like a resistor. Saturation acts like a near-constant current source.
• In saturation, current scales as the square of overdrive (V_gs − V_t) and linearly with W/L.
• Drive strength is tuned mainly through width W. Length is usually fixed at the process minimum.
• Channel-length modulation gives saturation a slight upward slope and finite output resistance.
• Velocity saturation breaks the square-law in short channels, making current more linear in overdrive.
• The body effect raises V_t when the source is above the body, which slows stacked transistors.
• DIBL lowers V_t at high drain voltage and is a short-channel leakage problem.
• Subthreshold current is exponential. The subthreshold slope (best 60 mV/decade) tells how sharply the device turns off.
• Lowering V_t boosts speed but raises leakage exponentially. This is the central speed-versus- power tradeoff.
• Heat lowers both mobility and V_t. On-current falls and leakage rises, so hot chips run slower and leakier.
• Gate capacitance has a useful channel part (C_ox × W × L) and parasitic overlap parts at the source and drain.