FinFET & Advanced Devices

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

When the Flat Transistor Ran Out of Road

For decades the transistor was a flat thing. The gate sat on top, the current flowed in a channel just under it. Making it smaller made chips faster and cheaper. But past a point, the flat shape stopped working well. The gate lost its grip on the channel. Leakage shot up. Something had to change. The answer was to stand the channel up and wrap the gate around it. That is the FinFET. Later came the gate-all-around device. This chapter explains why the flat device failed and how the new shapes fix it, in plain words.

Why the Planar Device Failed

In a flat transistor, the gate controls the channel from one side: the top. When the channel was long, that was plenty. But as the channel got short, the drain (the far terminal) started to have its own pull on the channel. The gate's single-sided grip was no longer in full control. This loss of control is called a short-channel effect. Two symptoms stand out. First, the device leaks current even when it should be off. Second, its threshold voltage (the gate voltage that turns it on) drifts with the drain voltage. Both are bad. Leakage wastes power; a drifting threshold makes the device unreliable.

Worked example — leakage explosion

Suppose each shrink generation roughly triples per-device leakage if the shape does not improve. Over three generations:

relative leakage = 3 × 3 × 3 = 27×

A 27-fold rise in leakage is unacceptable. The flat shape simply could not be shrunk further without drowning in leakage. A new structure was needed.

The FinFET Idea

A FinFET turns the channel on its side. The channel becomes a thin vertical fin of silicon. The gate then wraps over the top and down both sides of the fin. Now the gate controls the channel from three sides, not one. Three-sided control is far stronger. The gate can fully turn the channel off, even when it is short. Leakage drops. The threshold stays steady. This is the whole reason FinFETs took over: better gate control at small sizes.

Sizing With Fins

A flat transistor is sized by choosing its width: wider means more drive current. A FinFET cannot vary smoothly like that. The fin has a fixed height and width. You get more drive by adding more fins in parallel, not by widening one fin. So FinFET sizing is quantized. You choose 1 fin, 2 fins, 3 fins, and so on. Each fin adds a fixed chunk of drive. This changes how designers size cells: drive strength comes in steps, not a continuous range.

Worked example — drive in fin steps

One fin delivers 30 µA of drive at a given voltage. A gate needs about 80 µA.

fins needed = ceil(80 / 30) = ceil(2.67) = 3 fins
3 fins deliver 3 × 30 = 90 µA (a bit more than needed)

You cannot pick 2.67 fins. You round up to 3. That gives 90 µA, slightly overshooting the target. Quantized drive is a defining feature of fin-based design.

Gate-All-Around and Nanosheets

The next step wraps the gate all the way around the channel: gate-all-around (GAA). The channel becomes one or more thin horizontal sheets (nanosheets), with the gate completely surrounding each. Four-sided control is even stronger than three-sided. Nanosheets also bring back some sizing freedom. The sheet can be made wider, so drive is not as strictly quantized as with fins. This is why the industry moved from fins toward stacked nanosheets at the smallest nodes.

What Stays the Same — and What Changes

The logic does not change. An inverter is still a pull-up and a pull-down. A NAND is still series and parallel devices. The Boolean behaviour, the gate shapes, the delay and power ideas — all hold. A designer's mental model survives. What changes is the device underneath and the sizing rules. Drive comes in fin or sheet steps. Capacitances differ. The layout rules are tighter. And because gate control is better, lower voltages become usable, which helps power.

Worked example — voltage headroom

Better control lets the supply drop. Going from 0.9 V to 0.75 V on a fin device:

dynamic power ratio = (0.75 / 0.9)² ≈ 0.69
about a 31% dynamic-power saving

The stronger device tolerates the lower voltage without leaking out of control, so the chip banks the power saving.

Interview Q&A

controlling from only the top — lost its grip, and the drain began controlling the channel too. This caused short-channel effects: high off-state leakage and a threshold voltage that drifts with drain voltage, both of which worsen with every shrink.

top and both sides, giving three-sided control instead of one. The stronger grip fully turns the channel off even when short, cutting leakage and steadying the threshold.

sized by smoothly choosing its width; a FinFET gets more drive only by adding whole fins in parallel. So FinFET drive is quantized in fixed steps — you pick 1, 2, 3 fins — rather than any continuous width.

completely, often using stacked horizontal nanosheets, giving four-sided control — stronger than the FinFET's three. Nanosheets also allow adjustable channel width, restoring some of the sizing freedom that fins lost.

the same way and the delay/power concepts hold. What changes is the device underneath: quantized sizing, different capacitances, tighter layout rules, and the ability to run at lower voltage thanks to better control.

supply voltage, so the chip can drop its voltage. Since dynamic power scales with voltage squared, going from 0.9 V to 0.75 V saves roughly 31% of dynamic power — a saving the better device makes safe.

Key Takeaways

• The planar transistor failed at small sizes because one-sided gate control let leakage and threshold drift explode.
• The FinFET stands the channel up and wraps the gate on three sides for strong control and low leakage.
• FinFET drive is quantized in fins — you add whole fins, not a continuous width.
• Gate-all-around / nanosheets give four-sided control and restore adjustable width at the smallest nodes.
• The logic stays the same; sizing rules and the usable (lower) voltage change, helping power.