Glossary of CMOS Terms

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

How to Use This Glossary

This is a plain-language glossary of the terms used across this handbook. Each entry is short. It gives the idea, not a textbook definition. Use it to refresh a term fast before an interview, or to look up anything that was unclear in a chapter. Terms are grouped by theme so related ideas sit together.

MOSFET. The basic switch in a chip. A gate voltage turns a channel between two terminals on or off.

NMOS. A transistor that turns on with a high gate voltage and passes a strong low. The pull-down workhorse. PMOS. A transistor that turns on with a low gate voltage and passes a strong high. The pull-up partner; weaker than NMOS for the same size. Threshold voltage (Vt). The gate voltage at which a transistor starts to turn on. Low Vt is fast but leaky; high Vt is slow but low-leakage. Channel. The conducting path under the gate that carries current when the device is on. Drive strength. How much current a device or cell can push. More drive charges a load faster. Short-channel effects. Problems that appear when the channel gets very short: leakage and a drifting threshold, because the gate loses control. FinFET. A transistor with the channel stood up as a fin and the gate wrapped on three sides, for strong control at small sizes. Gate-all-around (GAA). A transistor with the gate fully surrounding the channel (often a stack of nanosheets) for even better control.

Logic and Gates

Static CMOS. Logic with a PMOS pull-up and NMOS pull-down network; the output is always firmly driven. Pull-up / pull-down network. The PMOS group that drives the output high; the NMOS group that drives it low. NAND / NOR. Basic gates. NAND stacks NMOS in series; NOR stacks PMOS in series, making NOR slower. Dynamic logic. Logic that precharges the output high then conditionally discharges it; faster and smaller but fragile. Domino logic. Dynamic gates chained safely by adding a static inverter after each. Pass-transistor logic. Logic that uses transistors as switches passing a signal; compact but gives degraded levels. Transmission gate. An NMOS and PMOS in parallel acting as a switch that passes both high and low well. Fan-in / fan-out. How many inputs a gate has; how many inputs one output drives. Finite state machine (FSM). A control circuit that holds a state and moves between states each clock edge.

Timing

Slew (transition time). How fast a signal rises or falls. Slow slew adds delay. Setup time. How long before the clock edge data must be stable. Violating it caps the clock speed. Hold time. How long after the clock edge data must stay stable. Violating it fails regardless of clock speed. Slack. How much a timing check passes by. Positive passes; negative fails. Critical path. The slowest path; it sets the maximum clock frequency. Skew. The difference in clock arrival time between two registers. Jitter. Random cycle-to-cycle wobble in where a clock edge lands. Logical effort. A quick method to size gates by splitting delay into gate type, fanout, and a fixed part. Pipelining. Splitting work across stages with registers between them to raise throughput.

Power

Dynamic power. Power burned when signals switch; grows with activity, load, and voltage squared. Leakage (static power). Power burned all the time because transistors never fully turn off; worsens with heat. Clock gating. Stopping the clock to an idle block to cut its dynamic power. Power gating. Cutting the supply to a block to remove its leakage; needs retention to keep state. Multi-Vt. Using fast leaky cells only on critical paths and slow low-leakage cells elsewhere. DVFS. Dynamic voltage and frequency scaling — lowering both when the workload is light to save power. Level shifter. A circuit that moves a signal between two voltage domains. Isolation cell. A cell that clamps a signal to a safe value when its source domain is powered off.

Interconnect and Physical

Interconnect. The metal wires connecting cells. Long wires add resistance and capacitance, hence delay. RC delay. Delay from a wire's resistance times its capacitance; grows with the square of unbuffered length. Repeater (buffer). A buffer inserted along a long wire to make its delay grow linearly, not as a square. Via. A small vertical metal plug connecting two metal layers.

Standard cell. A pre-made, fixed-height logic cell that tools place automatically in rows. Characterization. Measuring a cell's delay and power into lookup tables for the timing tools. Floorplanning. Deciding where big blocks, I/O, and power channels go on the chip. Placement. Deciding where each standard cell sits; sets wire lengths and thus timing. Routing. Drawing the metal connections between cells, global then detailed. Congestion. When more wires need a region than there are tracks; blocks routing. Design rule. A minimum width or spacing that guarantees the chip can be manufactured. IR drop. Voltage lost across the power grid; too much starves and slows distant cells. Electromigration. Metal atoms slowly moving under heavy current, which can eventually break a wire.

Memory

SRAM. Fast static memory holding each bit in cross-coupled inverters; no refresh, but area-hungry (6 transistors). DRAM. Dense memory storing each bit as charge on a tiny capacitor; needs periodic refresh. Word-line / bit-line. The wire that selects a memory row; the wire that carries a cell's data. Sense amplifier. A circuit that detects a small bit-line difference and snaps it to full logic levels. Write assist. Tricks that help bit-lines flip a stubborn cell at low voltage. Flash. Nonvolatile memory storing charge on a floating gate; keeps data with power off but wears with writes.

Manufacturing, Test, and Reliability

Yield. The fraction of made chips that work. Defects lower it. Fault model. A simple model of a defect (e.g. a node stuck at 0 or 1) used to generate tests. Scan chain. Flip-flops linked into a shift register so test patterns can be loaded and results read out. ATPG. Automatic test pattern generation — software that creates tests to catch modelled faults. BIST. Built-in self-test — on-chip logic that tests the chip itself. ESD. Electrostatic discharge — a static shock; pads need protection circuits to survive it. ECO. Engineering change order — a small late fix that avoids rebuilding the whole chip. Tape-out. Sending a finished, signed-off design to be manufactured.

Key Takeaways

• This glossary collects the handbook's terms in plain language, grouped by theme for fast review.
• Device terms (MOSFET, Vt, FinFET) underpin everything above them.
• Timing terms (setup, hold, slack, skew, jitter) recur in every performance discussion.
• Power and physical terms (leakage, IR drop, placement, routing) dominate modern design.
• Use it as a quick refresher — pair each term with its full chapter for depth.