Interview Q&A Bank — Advanced

STA fundamentals — cell delay, interconnect, setup/hold, MCMM, OCV, noise, IR-drop and sign-off

Advanced Bank — for the Second-Round Interviewer

These questions go past basic definitions. They test the why and the tricky corner cases. They separate someone who only read about STA (static timing analysis) from someone who has fixed timing on real chips. Each answer gives the reasoning. Many include a number.

Multi-Clock and Phase Relationships

waves over one shared window. That window is the least common multiple (LCM) of the two periods. It then lists every launch and capture edge pair. It picks the smallest setup gap and the tightest hold pair as the real checks.

Launch edges fall at 0, 5, 10, 15, 20, 25. Capture edges fall at 0, 6, 12, 18, 24, 30. The tool pairs each launch with the next capture after it. It keeps the worst (smallest) gap. Here that gap can be just 1 ns (launch at 5, capture at 6). Such a tiny constraint is why mismatched-speed interfaces are hard.

clock gives a shorter setup window. You often must hold or qualify the data across several fast cycles.

edge is now half a period away, not a full period. That makes it a half-cycle check. It is much tighter and easy to miss.

Generated, Gated, and Mutually Exclusive Clocks

edge link. That gives wrong capture edges. You usually see a huge fake violation or a fake pass. Always declare divide and multiply links.

asynchronous) clock group. The tool then skips checks between them. A clock mux's two sources are a common example.

must open and close cleanly. It must not chop or glitch the clock. The enable must stay stable around the gating edge.

make a tiny runt pulse. This happens if the enable changes at the wrong moment. Integrated clockgating cells latch the enable. That guarantees a clean gate with no glitch.

Time Borrowing and Latches

Data that arrives after the opening edge can still pass, if it lands in the open window. So the late stage borrows time from the next stage. The limit is the size of the open window.

length. Borrowed time can pass down a chain of latches. But once a stage uses up its window, the path fails. Endless borrowing in a report can hide a real problem.

This widens the window where a fast new value can race through. So you must check hold carefully against the closing edge.

Variation, Statistics, and Pessimism

derate by path depth and distance. Random variation averages out over more stages. So deep paths get a smaller derate than one flat number gives. This recovers margin that flat OCV throws away.

sigma (spread). The random sigmas add by root-sum-square along the path. Slack is taken at mean minus k times sigma, often 3 sigma. This is more accurate. It treats variation as statistics instead of worst-casing every stage.

Combined sigma = sqrt(5 × 10²) = about 22 ps, not 50 ps. At 3 sigma the path is 500 + 66 = 566 ps. A naive worst case would be 5 × 130 = 650 ps. The 84 ps of saved margin is the whole point of statistical timing.

removal) cancels false opposite derating on the shared clock trunk. Statistics stop the tool from worstcasing every independent stage. Together they remove huge pessimism. Without them you would over-design for no reason.

Crosstalk Deep Cuts

moving the same way and aligned can cancel coupling toward 0×. The victim speeds up, which hurts hold. A quiet aggressor is about 1×. An aggressor moving the opposite way pushes toward 2×. The victim slows down, which hurts setup.

windows depend on delays. So the tool loops between computing windows and deltas until they settle. This avoids both missed overlaps and impossible worst-case lineups.

The path just runs faster or slower. Functional noise is a glitch on a (often quiet) victim. That glitch can pass on a wrong value or upset a latch. It does not depend on the clock period.

trigger a wrong capture or a wrong reset. It corrupts state no matter what the data path does. So clock and async nets get the tightest noise limits and shielding first.

Asynchronous Crossings and Metastability

is no valid setup or hold check. STA marks the crossing as a false path. It relies on synchronizers for safety.

stage output to settle. This improves MTBF (mean time between failures) exponentially. It is still never infinite, though.

first synchronizer stage, for example its max delay or skew. That way a captured-but-metastable value gets the full cycle to settle before the second flop samples it.

cycles. So the receiver can see a mixed-up value. Multi-bit crossings need gray coding, a handshake, or an async FIFO to stay coherent.

Multicycle and Half-Cycle Corner Cases

MCP pushes the capture edge out by three cycles. Without the hold MCP, the default hold check lands one edge before that. That is two cycles too tight. A hold MCP of 2 pulls it back to the correct adjacent edge.

captures on the next falling edge. Negative-edge flops can also cause it. The data gets only half a period. That is very tight and easy to miss. You must spot it so it is not relaxed by accident.

Hierarchy, Power, and Sign-off

arcs only) for the most compression on stable interfaces. Use an interface logic model (real boundary gates kept) when interface accuracy matters. OCV is the main reason. It needs real path depth to derate right.

corner it was built at. Use it at a corner it does not cover and you get wrong numbers. A missing-corner model is a classic hierarchical sign-off bug.

Lower voltage means more delay. You handle it with a margin or derate. The accurate way annotates per-cell voltages from a power run and recomputes delays. That is voltage-aware timing.

(I·R plus L·di/dt). It comes from many cells switching at once. It is worst at clock edges. A different droop on the launch and capture clock branches makes IR-induced skew. That acts like extra jitter.

(clocks, I/O delays, exceptions). You need valid MCMM (multi-corner multi-mode) views with matched libraries and parasitics. CPPR must be on. SI (signal integrity) should be on where it matters. You must also check for unconstrained paths. Only then are the slacks real.

Scenario-Style (think aloud)

Not real. It was shared-trunk pessimism. Trust the CPPR result. Only a violation that remains after CPPR is genuine.

for temperature inversion. At low voltage the slow-cold corner can be the true setup-worst. Confirm your corner set actually includes that inverted case. Do not just assume slow-hot.

cells traded speed for less leakage. That ate into the slack. Run a focused setup-recovery pass. Swap just those few cells back to faster Vt. Keep the rest of the leakage savings.

make all bits settle in the same cycle. So the multi-bit value can be incoherent. Use gray coding, a handshake, or a FIFO instead.

data delay shortest. Add skew and that is the classic hold-worst corner. Fix it with hold buffers or mindelay control. Then confirm setup at the slow corner is still clean.

Advanced Quick Reference

Key Takeaways

• Master the multi-clock LCM expansion and the multicycle hold-MCP bookkeeping. Both are favourite traps.
• Explain the AOCV/POCV math (depth averaging, RSS sigma). Show why CPPR plus statistics cut pessimism.
• Know the crosstalk switching-factor model and the iterative window loop.
• Be fluent on async and metastability. Know why STA false-paths it, why extra flops help, and how multi-bit stays coherent.
• For scenarios, always split real violations from pessimism or constraint artifacts before you propose a fix.