On-Chip Variation & Timing Derate

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

On-Chip Variation & Timing Derate

A corner sets one process, voltage, and temperature for the whole chip. But the chip is not uniform inside. One part of the die may be a touch faster than another. The supply may droop more in one corner of the floorplan. Two gates that share a library number can still differ in real silicon. This spread within a single die is called "on-chip variation," often shortened to OCV. Because of this spread, timing must allow a margin. You cannot assume two paths share the exact same delay just because they use the same cells. One may run faster, one slower. Timing derate is the tool for adding this margin. This chapter explains the variation, the derate command, early versus late factors, why a correction called CPPR matters, and the difference between flat and advanced derate.

What On-Chip Variation Means

On-chip variation is the difference in delay between identical cells placed in different spots on one die. The library gives a single delay for a cell at a corner. Real cells scatter around that number. Some are a bit quick. Some are a bit slow. The scatter comes from tiny process differences, local voltage droop, and small temperature gradients across the die. This matters most when a path's launch and capture share part of their journey but then split. Picture a clock that travels through a shared trunk, then branches to a launch flop and a capture flop. The

shared trunk delay is common to both. After the branch, the two clock paths differ. Variation can make one branch faster and the other slower at the same instant.

Variation has two flavors. One flavor is systematic. It shifts a whole region the same way, such as a voltage droop that slows one corner of the die. The other flavor is random. It scatters cell by cell with no pattern. Derate is a blunt way to cover both. It does not know which cells are fast and which are slow. So it adds margin to all of them and trusts that the margin covers the true spread. That is why derate is conservative by nature: it protects against a worst case that may never line up exactly.

Early and Late Derate

To model variation, the tool scales delays by a factor. This is "derate." A derate factor near 1.0 means little change. A factor above 1.0 stretches a delay. A factor below 1.0 shrinks it. You apply derate so that, within one analysis, some paths are treated as slow and some as fast at the same time. There are two directions. "Late" derate makes a path slower. "Early" derate makes a path faster. For a setup check, the data path should be late and the capture clock should be early. That is the pessimistic mix for setup. For a hold check, the directions swap.

# standard SDC — portable across compliant tools
# late paths run 3.4 percent slow, early paths run 2.1 percent fast
set_timing_derate -late 1.034
set_timing_derate -early 0.979

The first line stretches late paths by 3.4 percent. The second line shrinks early paths by 2.1 percent. The tool applies the right one to each path in each check. The exact numbers come from your variation study; the values here are invented for illustration. You can scope derate to clocks, data, cells, or nets. Scoping lets you derate the clock network differently from the data logic. Some flows derate clock and data with separate factors because the clock tree behaves differently.

# standard SDC — portable across compliant tools
set_timing_derate -late 1.041 -clock -cell_delay
set_timing_derate -early 0.974 -data -cell_delay

behavior is tool-specific, treat the reporting and the fine-grained controls as illustrative, even though the base command is portable.

When launch and capture clocks share a common trunk, derate can be too harsh. The tool might make the shared trunk slow for one path and fast for the other at the same time. But it is the same physical wire. The same wire cannot be both slow and fast at one instant. Treating it both ways adds pessimism that is not real. The fix is "common path pessimism removal," or CPPR. It is also called clock reconvergence pessimism removal. CPPR finds the shared part of the launch and capture clock paths. Then it cancels the derate difference on that shared part. Only the part after the branch keeps its variation margin. This gives a fair, less pessimistic result. A worked illustration. A setup path has a launch clock that travels 0.612 ns through a shared trunk, then 0.188 ns down its own branch. The capture clock travels the same 0.612 ns trunk, then 0.205 ns down its branch. Without CPPR, derate makes the trunk slow for one and fast for the other, adding a fake gap of about 0.024 ns. With CPPR, that 0.024 ns of false pessimism is removed because the trunk is shared. The path's slack improves by 0.024 ns, and that improvement is honest, not a trick.

There are two styles of applying derate. The simple style is "flat" derate. You pick one late factor and one early factor and apply them everywhere. Every cell on a late path gets the same stretch. Every cell on an early path gets the same shrink. Flat derate is easy to set and easy to explain. But flat derate can be too crude. A long path passes through many cells. Variation tends to average out over many cells, because some are fast and some are slow and they partly cancel. A short path has fewer cells, so it has less averaging. Flat derate ignores this. It applies the same percentage whether the path has 3 cells or 30 cells. "Advanced" derate adjusts the factor based on path depth or distance. A deeper path, with more cells, gets a smaller effective derate because variation averages out. A shallow path gets a larger one. This matches the physics better. The result is less pessimism on long paths and proper margin on short ones.

# illustrative — names vary by tool
# advanced derate setup is often driven by tables outside the SDC
set_advanced_derate_mode on
report_timing -derate -nworst 8

The exact form of advanced derate, and the data tables it needs, vary widely by tool. The concept is portable: deeper paths deserve less derate. The commands and tables are not portable, so treat them as illustrative. A worked illustration. A short path of 4 cells and a long path of 26 cells both use a flat late factor of 1.034. The short path gains 0.030 ns of margin from derate; the long path gains 0.214 ns. Under advanced derate, the long path's effective factor drops to about 1.019 because its variation averages out. Its added margin falls to roughly 0.121 ns, which is more realistic. The short path keeps close to its full factor because it has little averaging. Advanced derate thus frees the long path from false pessimism while keeping the short path honest.

How Derate Fits the Overall Flow

Derate is one piece of total timing margin. It sits alongside clock uncertainty and corner choice. Clock uncertainty already covers jitter and some skew. Derate covers on-chip variation. You must avoid double counting. If uncertainty already holds variation margin, your derate factors should be small or near 1.0. If derate carries the variation, uncertainty should hold only jitter. Decide once where each margin lives.

A clean flow states the plan in one place. For example: corners bound the global PVT; uncertainty holds jitter only; derate holds variation; CPPR removes shared-path pessimism. With that plan written down, every reviewer knows where each margin comes from and no margin gets counted twice. As a design matures, the derate values usually shrink. Early in a project you know little about the real silicon, so you set large factors to stay safe. Later, after measured data arrives, you can tighten the factors to match what the chip actually does. Shrinking derate late in the flow can recover slack that was only ever lost to over-caution. The reverse is also true: if early measurements show more variation than expected, you raise the factors before signoff rather than after.

# standard SDC — portable across compliant tools
# variation in derate, jitter in uncertainty, no overlap
set_timing_derate -late 1.028 -early 0.982
set_clock_uncertainty 0.057 [get_clocks core_clk]

The derate carries variation. The uncertainty of 0.057 ns carries jitter. The two do not overlap. This separation keeps the total margin honest and easy to defend in review.

Interview Q&A

on one die. Local process, voltage, and temperature differences make some cells faster and some slower than the single library value, so timing must allow margin for the spread.

faster. For setup, the data path is made late and the capture clock early. For hold, the directions swap. This creates the pessimistic mix for each check.

wire as both slow and fast at once. That is false pessimism. CPPR cancels the variation on the shared segment so only the after-branch portion keeps margin.

ignoring path depth. Advanced derate shrinks the factor for deeper paths because variation averages out over many cells. Advanced derate is more realistic but needs extra data and is tool-specific.

both carry it, the design is over-margined and may be hard to close. Decide once that uncertainty holds jitter and derate holds variation, so each margin is counted only once.

and some are slow, so their variations partly cancel. A short path has fewer cells and less cancellation. Advanced derate gives the deep path a smaller factor to match this averaging.

Key Takeaways

• On-chip variation is the delay spread between identical cells on one die, and timing must add margin because the single library value is not exact everywhere.
• Late derate slows a path and early derate speeds it up, combined to form the pessimistic mix for setup and the opposite mix for hold.
• CPPR removes false pessimism on the shared clock trunk, because one physical wire cannot be both fast and slow at the same instant.
• Advanced derate shrinks the factor for deeper paths, matching how variation averages out over many cells better than a flat factor.

• Derate, clock uncertainty, and corners must not overlap, so decide once where variation, jitter, and global PVT margin each live.