Generated & Derived Clocks

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

What a Generated Clock Is

Many chips make new clocks from an existing one. A divider halves a clock. A multiplier doubles it. A gate turns it on and off. Each of these makes a clock that depends on a master clock (the source clock it is built from). A generated clock is a clock derived from a master clock. You define it with create_generated_clock . The key idea is that it is linked to its master. When the master changes, the generated clock follows automatically. This linking is the whole point. You do not invent a fresh, independent clock. You tell the tool, "this clock is built from that one, by dividing or multiplying." The tool then knows the two are related and times paths between them correctly.

The most common generated clock is a divided clock. A divide-by-2 of a 2.0 ns master clock produces a 4.0 ns clock. The generated clock is slower, but it is still tied to the master's edges.

Defining a Generated Clock

The create_generated_clock command needs the new clock's name, its source pin, and a description of how it relates to the master. The relationship is usually a divide or multiply factor. The source pin is where the generated clock appears, typically the output of the divider or gate cell. The -source option points back to the master clock's pin. This is the link that keeps the two clocks related.

# standard SDC — portable across compliant tools
# A divide-by-2 generated clock from a 2.0 ns master
create_clock -name ref_clk -period 2.0 [get_ports clk_in]
create_generated_clock -name div2_clk \
-source [get_ports clk_in] \
-divide_by 2 \
[get_pins div_reg/Q]

This says: ref_clk is the 2.0 ns master at clk_in. div2_clk is generated at the divider's Q pin, by dividing ref_clk by 2, giving a 4.0 ns period. You never write 4.0; the tool computes it from the divide factor.

Divided and Multiplied Clocks

A divided clock runs slower than its master. Divide-by-2 doubles the period. Divide-by-4 quadruples it. The factor tells the tool how many master cycles make one generated cycle.

# worked example — divided clock periods
Master ref_clk period:   2.0 ns
Divide-by-2 -> 2.0 x 2 = 4.0 ns generated period
Divide-by-4 -> 2.0 x 4 = 8.0 ns generated period

A multiplied clock runs faster than its master. Multiply-by-2 halves the period. These usually come from a clock-generating circuit that speeds up an input clock. The factor tells the tool how many generated cycles fit in one master cycle.

# worked example — multiplied clock periods
Master ref_clk period:   2.0 ns
Multiply-by-2 -> 2.0 / 2 = 1.0 ns generated period
Multiply-by-4 -> 2.0 / 4 = 0.5 ns generated period

The big advantage is that you state intent, not a hard number. You say "divide by 2," and the tool computes 4.0 ns. If the master period later changes to 2.4 ns, the generated clock becomes 4.8 ns automatically. Nothing breaks.

A generated clock's edges line up with its master's edges. This edge relationship is what makes timing between the two clocks correct. The tool knows exactly which master edge produced which generated edge. For a divide-by-2, the generated clock rises on every second master rising edge. The two clocks share a common origin in time. This shared origin lets the tool check paths that cross between the master and the generated clock.

This is why deriving beats redefining. If you instead declared a separate 4.0 ns clock with

create_clock  at the divider output, the tool would treat it as unrelated to the master. It would lose the

edge alignment, and paths crossing the two clocks would be checked wrongly. You can fine-tune which edges to use with extra options, for cases like inverted or shifted generated clocks. But the default edge alignment from the divide or multiply factor covers most designs and is the safest starting point.

Common Mistakes

The first common mistake is redefining instead of deriving. Engineers sometimes put a plain

create_clock  on a divider output to "just set the period." This severs the link to the master. The tool

then sees two unrelated clocks and mistimes every crossing path. The second mistake is a wrong source pin. The -source must point at the master clock's pin, and the source pin in the command must be where the generated clock actually appears. Swapping these, or pointing at the wrong cell, gives a generated clock that does not match the hardware. The third mistake is forgetting the master entirely. A generated clock needs its master to exist first. If you define div2_clk before ref_clk, the command has nothing to derive from and fails or warns.

# standard SDC — portable across compliant tools
# WRONG: redefining the divider output as an independent clock
# create_clock -name div2_clk -period 4.0 [get_pins div_reg/Q]
# This breaks the link to the master and mistimes crossings.
# RIGHT: derive it so the link to ref_clk is preserved
create_generated_clock -name div2_clk \
-source [get_ports clk_in] -divide_by 2 [get_pins div_reg/Q]

A fourth mistake is a mismatched factor. If the hardware divides by 4 but the constraint says divideby-2, the tool builds a 4.0 ns clock while the chip runs at 8.0 ns. Reports pass against the wrong period, and the chip can fail in silicon.

Interview Q&A

with create_generated_clock . It is linked to its master, so when the master period changes, the generated clock follows automatically. Dividers, multipliers, and clock gates all produce generated clocks.

relationship to the master. A plain create_clock on a divider output makes an unrelated clock, so the tool loses edge alignment and mistimes every path crossing between the two clocks. Deriving preserves the link.

2.0 ns master divided by 2 gives a 4.0 ns generated clock. You never write 4.0 yourself; the tool computes it from the -divide_by 2 option, so it stays correct if the master changes.

1.0 ns generated clock, which runs twice as fast. These usually come from a clock-generating circuit that speeds up the input clock.

hardware divides by 4 but the constraint says divide-by-2, the tool checks against a 4.0 ns clock while the chip really runs at 8.0 ns. Reports pass against the wrong period and the chip can fail.

generated clock has nothing to derive from if the master does not exist, so the command fails or warns. Always define the primary clock with create_clock before any create_generated_clock that uses it.

Key Takeaways

• A generated clock is derived from a master with create_generated_clock and stays linked to it.
• Use -divide_by and -multiply_by to state intent; the tool computes the period, so a 2.0 ns master divided by 2 becomes 4.0 ns.
• Edge alignment to the master is what makes cross-clock paths time correctly, which is why deriving beats redefining.
• Never redefine a divider output with create_clock; it severs the link and mistimes crossings.
• Match the factor and source pins to the real hardware, and define the master first, or reports pass against the wrong period.