Multicycle Paths

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

Multicycle Paths

By default the timing tool gives every path exactly one clock cycle. Data launched on one edge must be captured on the very next edge. But some paths do not need to be that fast. The design may guarantee, by its own logic, that the data is only used several cycles later. Forcing those paths into one cycle wastes effort and area. A multicycle path is a path the design allows more than one cycle to complete. A cycle is one clock period. The SDC constraint format relaxes such paths with

set_multicycle_path . Used correctly it lets slow logic settle over several cycles. Used carelessly it

creates a famous trap: the hold check moves to the wrong edge and silently breaks. This chapter walks through both the relaxation and the trap, with a worked edge example. The key idea is that setup and hold are checked relative to clock edges. When you move the setup edge, you must usually move the hold edge to match, or you create an impossible hold requirement. A helpful way to picture it: setup and hold are a pair of fences that bracket the launched data. The setup fence sits ahead, marking the latest the data may arrive. The hold fence sits behind, marking the earliest the data may change. By default these two fences are one cycle apart and snug against the launch. A multicycle relaxation slides the setup fence forward by several cycles. The trap is that the hold fence tries to follow it, drifting forward too, and ends up demanding the data stay frozen across nearly all those cycles. The hold multicycle is how you nail the hold fence back where it started.

Paths Allowed More Than One Cycle

Some logic is deliberately slow but is only sampled occasionally. A large arithmetic unit might take parts of three cycles to finish, while a control signal guarantees its result is only read on the third cycle. Holding that unit to one cycle would force needless speed-up. A multicycle path tells the tool the real number of cycles.

set_multicycle_path  takes a multiplier, the number of cycles. A value of 3 means the setup check

uses the third capture edge instead of the first. The -setup option says the multiplier applies to the setup check. You scope it with -from , -to , and -through , just like a false path.

# standard SDC — portable across compliant tools
# Allow this slow datapath three cycles for setup
set_multicycle_path 3 -setup -from [get_pins mult_a_reg/Q] -to [get_pins prod_reg/D]

With a 4.00 ns period and a 3-cycle setup multiplier, the data has 3 × 4.00 = 12.00 ns to arrive instead of 4.00 ns. That is a large relaxation, only valid if the logic truly does not use the result sooner.

To understand the trap you must see where each check lands by default. Setup is checked at the next capture edge after launch, edge 1. Hold is checked one edge before the setup edge, at edge 0, the same edge as launch. This pairing keeps the hold window right next to the launch. When you set a setup multiplier of N, the setup edge moves to edge N. But the hold check, by default, follows the setup edge and lands at edge N-1. That is the problem. You wanted hold to stay near launch, at edge 0, but now it sits at edge N-1, demanding the data hold stable for almost N full cycles. No path can meet that, so it fails.

The Classic Trap and the N-1 Fix

The fix is to also relax the hold check by N-1 cycles, pulling the hold edge back to edge 0 where it belongs. You apply a hold multicycle of N-1 with the -hold option. For a setup multiplier of 3, you set a hold multiplier of 2. The arithmetic: setup edge is at N = 3. Default hold edge is at N - 1 = 2. Moving hold back by 2 lands it at edge 0. So the hold multiplier you need is N - 1 = 2. This is the rule of thumb: a setup multicycle of N almost always needs a matching hold multicycle of N - 1.

# standard SDC — portable across compliant tools
# Setup multiplier 3 needs hold multiplier N-1 = 2
set_multicycle_path 3 -setup -from [get_pins mult_a_reg/Q] -to [get_pins prod_reg/D]
set_multicycle_path 2 -hold  -from [get_pins mult_a_reg/Q] -to [get_pins prod_reg/D]

Forgetting the hold line is the single most common multicycle mistake. The setup relaxation looks fine, the path passes setup easily, but the hold check now requires the data to stay stable for nearly two whole cycles, which is impossible for normal logic. The tool either reports a huge hold violation or, worse if hold is unchecked, lets a real hold failure through.

Let period be 4.00 ns. Launch edge is at time 0.00 ns. The slow datapath delay is 9.50 ns. Setup time is 0.15 ns. We use a setup multiplier of 3 and a hold multiplier of 2.

# Worked setup with multicycle 3
Setup capture edge = 3 x period = 3 x 4.00 = 12.00 ns
Minus setup time              = -0.15 ns
Required time                 = 11.85 ns
Arrival (datapath delay)      =  9.50 ns
Setup slack = 11.85 - 9.50    = +2.35 ns   -> PASS

Without the multicycle, the setup edge would be at 4.00 ns and required time 3.85 ns, far less than the 9.50 ns arrival, giving slack of 3.85 - 9.50 = -5.65 ns, a big fail. The multicycle is what makes the path legal. Now hold. The shortest datapath delay is 0.50 ns. Hold time is 0.08 ns. With the hold multiplier of 2, the hold edge is pulled back to edge 0, at time 0.00 ns.

# Worked hold with multicycle 2 (hold edge at edge 0)
Hold capture edge = 0.00 ns
Plus hold time    = 0.08 ns
Required time     = 0.08 ns
Arrival (shortest path) = 0.50 ns
Hold slack = 0.50 - 0.08 = +0.42 ns   -> PASS

If we had forgotten the hold multiplier, the hold edge would sit at edge 2 = 8.00 ns. Required time would be 8.00 + 0.08 = 8.08 ns, while arrival is only 0.50 ns. Hold slack would be 0.50 - 8.08 = -7.58 ns, a massive false failure.

Multicycle paths are valid only when the design genuinely guarantees the result is not used for several cycles. That guarantee usually comes from an enable signal, a state machine, or a counter that gates when the destination flip-flop loads. If no such guarantee exists, a multicycle path is a lie and will cause functional failure.

Common valid uses: slow arithmetic blocks read every few cycles, slow interfaces clocked by an enable, and data sampled by a divided clock. Common abuse: slapping a multicycle on a failing path just to make the report green. That hides a real problem and risks silicon failure.

to complete. A setup multiplier of 3 moves the setup capture edge to the third edge, giving 3 cycles of arrival time instead of 1. It is valid only when the design guarantees the result is not used sooner.

the setup edge by default. With a setup multiplier of N, the hold edge lands at edge N-1 instead of near launch. That demands almost N cycles of stability, which fails. A hold multiplier of N-1 pulls the hold edge back to edge 0.

at edge 4; the default hold edge would be at edge 3. A hold multiplier of 3 moves the hold edge back to edge 0, restoring the normal hold window.

setup slack? Setup edge is 3 × 4.00 = 12.00 ns. Required time is 12.00 - 0.15 = 11.85 ns. Arrival is 9.50 ns. Slack is 11.85 - 9.50 = +2.35 ns. It passes, where one cycle would have failed badly.

at edge N-1. With a 4.00 ns period and N=3, the hold edge sits at 8.00 ns, requiring data to stay stable that long. With a 0.50 ns shortest path, hold slack is 0.50 - 8.08 = -7.58 ns, a large false hold violation.

functional guarantee that the result waits. If you add a multicycle just to silence a failing path, the silicon will still use the data in one cycle and fail. Valid multicycles always rest on an enable, state machine, or divided clock.

Key Takeaways

• A multicycle path grants a path more than one cycle; a setup multiplier of 3 gives 3 cycles of arrival time.

• The hold check follows the setup edge, so a setup multiplier of N strands the hold edge at edge N-1.
• The fix is a matching hold multicycle of N-1, pulling the hold edge back to launch (edge 0).
• Forgetting the hold line creates a huge false hold violation, often several cycles of impossible stability.
• Multicycles are valid only when the design guarantees the result waits; forcing a failing path green is abuse.