Latch-Based Timing & Time Borrowing

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

Latch-Based Timing & Time Borrowing

Most timing talk is about flip-flops. A flip-flop captures data on a clock edge. It is edge-triggered. But there is another storage element: the latch. A latch is level-sensitive. It does not wait for an edge. It passes data through while the clock is at one level, and holds when the clock is at the other. This difference changes timing in a big way. Latches allow time borrowing. Borrowing lets a slow stage steal time from a fast one. It can save a tight design. But it also makes the timing harder to reason about, especially for hold. SDC, the timing constraint format that compliant tools read, handles latches automatically once clocks are set. We never expand the letters; we say SDC. This chapter explains level sensitivity, the transparent phase, how borrowing works and its limit, and why hold is trickier with latches.

A latch watches the clock level, not the edge. Take a latch that is active high. When the clock is high, the latch is transparent. Transparent means the input flows straight to the output. Any change at the input shows at the output almost at once. When the clock goes low, the latch is opaque. Opaque means it holds the last value and ignores the input. So a latch has two phases each clock cycle. The transparent phase, when clock is high, and the opaque phase, when clock is low. The data is actually captured at the closing edge, the moment the latch goes opaque. Whatever value is present at that closing edge gets held. Compare this to a flip-flop. A flip-flop has no transparent phase. It samples once, at one edge, and holds the rest of the cycle. The latch's open window is what makes borrowing possible. Because the latch keeps listening during the transparent phase, data is allowed to arrive late, even after the opening edge, as long as it settles before the closing edge.

Suppose the clock period is 5.46 ns with a fifty percent duty cycle. Duty cycle is the fraction of the period the clock is high. The transparent phase is then 2.73 ns long. During those 2.73 ns the latch is open. That open window is the resource borrowing draws from.

How Time Borrowing Works

Time borrowing means a stage uses part of the next stage's time. It works because of the transparent phase. Normally a flip-flop demands that data arrive before its edge. A latch is gentler. It only demands

that data arrive before its closing edge, the end of the transparent phase. So data can arrive a little late, after the opening edge, and still be captured. That lateness is borrowed time. Walk through it. Stage one feeds a latch. Ideally data arrives by the latch's opening edge. But stage one's logic is slow and the data arrives 0.90 ns after the opening edge. With a flip-flop this would be a setup failure. With a latch, the latch is still transparent, so the late data passes through. The latch borrowed 0.90 ns from the time the next stage would have had. Where does that borrowed time go? The next stage starts later, because the data left the latch later. So the next stage now has 0.90 ns less time. Borrowing does not create time. It moves time from a fast stage to a slow stage. If the next stage had slack to spare, the move is free. The whole pipeline still works as long as no single stage overruns its limit.

# standard SDC — portable across compliant tools
# define the clock; the tool models the latch transparent window from it
create_clock -name pipe_clk -period 5.46 [get_ports pipe_clk]

A worked example makes it concrete. The period is 5.46 ns. A stage of logic needs 6.10 ns, which is 0.64 ns too long for a flip-flop. Feed it into an active-high latch. The latch stays open through its 2.73 ns transparent phase. The data, arriving 0.64 ns late, lands well inside that open window. The latch captures it at the closing edge. The 0.64 ns is borrowed from the next stage. If the next stage only needed 4.50 ns, it can spare the 0.64 ns and still finish in time.

Borrowing is not unlimited. There is a hard cap. A latch can only borrow up to the length of its transparent phase. It cannot borrow past its closing edge, because once the latch is opaque the input is ignored. So the most a latch can borrow is the open window. If the transparent phase is 2.73 ns, the latch can absorb data that is up to 2.73 ns late, minus a small setup margin at the closing edge. Setup margin is the time the data must be steady before the latch closes. Say that margin is 0.18 ns. Then the real borrowing limit is 2.73 minus 0.18, which is 2.55 ns.

If a stage needs more than the limit, borrowing cannot save it. The data arrives after the latch has closed. The latch holds the old value. The new data is lost or captured a full cycle late. That is a real timing failure, not a borrow.

There is also a chain effect. Borrowing can pass along a pipeline of latches. Stage one borrows from stage two, which borrows from stage three. Each link is fine alone. But the borrowing accumulates. If too many stages lean on the next, the last stage runs out of room. So the tool tracks borrowing across the whole chain, not just one latch.

Constraining Latch-Based Paths

The pleasant part is that you do not write special borrowing commands. Once the clocks are defined, the timing tool knows the latch's transparent phase from the clock waveform. It computes the open window. It then allows borrowing up to the limit on its own. The clock definition does the heavy lifting. What you must get right is the clock. The latch's transparent phase comes straight from the clock's high and low times. If the duty cycle is wrong in your clock definition, the open window is wrong, and borrowing is mismodeled. So define the clock period and its waveform carefully. The waveform sets when the clock rises and falls, which sets when the latch opens and closes.

# standard SDC — portable across compliant tools
# an explicit waveform: rises at 0, falls at 2.73, period 5.46
create_clock -name lat_clk -period 5.46 -waveform {0 2.73} [get_ports lat_clk]

If you ever want to forbid borrowing on a path, you can limit it. Some flows let you cap the borrowed time, even to zero, to force a path to behave like an edge-triggered one. This is useful when you do not trust the borrowing margin or want a predictable handoff. But the default is to let the tool borrow up to the natural limit.

# illustrative — names vary by tool
# report how much time each latch borrowed
report_timing -path_type full_clock -borrow

The reporting is where you watch borrowing. A timing report on a latch path shows the borrowed amount. If a latch borrows close to its limit, that is a warning sign. It means little margin is left, and a small change could tip it into failure. Healthy designs borrow modestly, not to the edge of the window.

Why Hold Is Trickier with Latches

Setup with latches is forgiving, thanks to borrowing. Hold is the opposite. Hold gets harder and more confusing with latches. Hold means data must stay steady long enough after capture, so the latch does not grab the next, new value too early. The problem is the open window. While the latch is transparent, it is listening the whole time. New data racing in during the transparent phase can pass straight through to the output. If the next stage's data arrives during this window, it can corrupt the value the latch was supposed to hold. With a flip-flop, the capture happens at one instant, so the hold window is narrow. With a latch, the latch is open for a long stretch, so fast new data has a long chance to sneak through. This means hold checks for latches reference the opening edge and the whole transparent phase, not just one moment. A fast path between two latches can fail hold because data arrives while the receiving latch is still open. Fixing it often means adding delay, so the new data does not arrive until after the latch has closed.

A worked example shows the danger. Two latches sit back to back. The clock period is 5.46 ns, transparent phase 2.73 ns. A short path between them has only 0.40 ns of delay. The second latch opens at the same edge the first one's data updates. With just 0.40 ns of delay, the new data reaches the second latch while it is still open, 2.33 ns before it closes. The second latch passes the new value straight through, losing the value it should have held. That is a hold failure caused by the open window, and it would need added delay to fix.

Interview Q&A

edge. A latch is level-sensitive: it is transparent while the clock is at one level and opaque at the other. During the transparent phase the input flows straight to the output, and the value is captured at the closing edge.

open and passes input to output. For an active-high latch it is when the clock is high. Its length comes from the clock's duty cycle. This open window is what makes time borrowing possible.

opening edge. So data can arrive late, after the latch opens, and still be captured. That lateness is borrowed from the next stage, which then starts later. Borrowing moves time from a fast stage to a slow one; it does not create time.

transparent phase, minus a small setup margin at the closing edge. It cannot borrow past its closing edge, because once opaque it ignores the input. Beyond that limit the data is lost or captured a full cycle late.

the tool derives the transparent phase and allows borrowing up to the limit automatically. The key is an accurate clock waveform, since the duty cycle sets the open window. You can optionally cap borrowing if you want a predictable handoff.

during the transparent phase can pass straight through and corrupt the held value. A flip-flop captures at one instant with a narrow hold window, while a latch's wide open phase gives fast new data a long chance to sneak through.

Key Takeaways

• A latch is level-sensitive, transparent while the clock is at one level and opaque at the other, capturing data at its closing edge.
• The transparent phase enables time borrowing, letting late data still be captured by moving time from a fast stage to a slow stage.
• Borrowing is capped at the open window minus a setup margin; data arriving after the latch closes is a real failure, not a borrow.
• You write no special borrowing command; an accurate clock period and waveform let the tool model the open window and borrow automatically.
• Hold is trickier with latches because the long open phase lets fast new data pass straight through, so latch hold often needs added delay.