Generated Clocks — Advanced Cases

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

Generated Clocks — Advanced Cases

Many clocks on a chip are not driven from outside. They are made on-chip from another clock. A divider circuit slows a clock down. A multiplier speeds it up. An inverter flips it. A piece of logic can even build a brand-new clock from existing edges. These derived clocks are called generated clocks. This chapter covers the advanced cases: divide, multiply, inversion, edge-derived, and combinational generated clocks, plus the master-source link and the errors that trip people up. A generated clock is a clock whose timing is defined relative to another clock, called the master clock. The master clock is the source. The generated clock inherits the master's edges and then transforms them. Because the relationship is fixed and known, the timing tool can treat the two as synchronous and time paths between them. This is different from defining a fresh clock, which would have no known relationship to the master. In SDC (the timing constraint format), you create these with create_generated_clock . You name the new clock, point it at the master source pin, and describe the transform: divide by some number, multiply by some number, invert, or derive from specific edges. The master-source link is the most important part. If it points at the wrong pin, the whole relationship is wrong.

Divide and Multiply

The most common generated clock is a divided clock. A divide-by-2 clock toggles once for every two master edges, so its period is twice as long. If the master clock has a period of 2.64 ns, a divide-by-2 generated clock has a period of 5.28 ns. You describe this with the -divide_by option.

# standard SDC — portable across compliant tools
# A divide-by-2 clock from a 2.64 ns master.
create_clock -name clk_ref -period 2.64 [get_ports clk_ref_in]
create_generated_clock -name clk_div2 \
-source [get_ports clk_ref_in] -divide_by 2 \
[get_pins div_reg/Q]

The generated clock lives at the output pin of the divider circuit, usually a flip-flop's Q output. The - source points back to the master. The tool then knows that two edges of clk_ref make one edge of clk_div2 . A multiply works the other way. A -multiply_by 2 clock has half the period, used when a circuit like a phase-locked structure produces a faster output. From a 2.64 ns master, a multiply-by-2 clock has a period of 1.32 ns.

The table shows several transforms from the same 2.64 ns master.

Inversion and Edge-Derived Clocks

Sometimes the generated clock is the master, inverted. An inverted clock rises where the master falls. You add -invert to the create command. The period stays the same, but every edge flips. This matters because registers clocked by the inverted clock capture on the opposite edge of the master's registers, which changes which edge pairs the tool checks.

# standard SDC — portable across compliant tools
# An inverted version of the master clock, same period.
create_generated_clock -name clk_inv \
-source [get_pins buf_cell/A] -divide_by 1 -invert \
[get_pins inv_cell/Z]

A more advanced case is an edge-derived clock. Instead of a simple divide, you tell the tool exactly which master edges become the generated clock's edges, using the -edges option. You list edge numbers of the master. Edge 1 is the first rising edge, edge 2 the first falling edge, edge 3 the second rising, and so on. The generated clock's rising, falling, and next rising edges come from the three edge numbers you list. Suppose the master has a period of 3.40 ns rising at 0 and falling at 1.70 ns. Its edges are numbered: edge 1 at 0, edge 2 at 1.70, edge 3 at 3.40, edge 4 at 5.10, edge 5 at 6.80. If you write -edges {1 3 5} , the generated clock rises at edge 1 (0 ns), falls at edge 3 (3.40 ns), and rises again at edge 5 (6.80 ns). That gives a period of 6.80 ns, a divide-by-2 built from chosen edges. The -edges form lets you make odd duty cycles and unusual phase shifts that a plain divide cannot.

Combinational Generated Clocks

Not every generated clock comes from a flip-flop. Sometimes a clock passes through pure combinational logic, like a multiplexer that selects between two clocks, or a chain of gates. A combinational generated clock is one whose source pin is the output of such logic, not a register. The clock is not divided or multiplied; it is the same clock that simply traveled through gates. You still use create_generated_clock , often with -divide_by 1 , to tell the tool that the signal at the gate output is a clock related to the master. Without this, the tool would not know the gate output carries a clock, and it would mistime or drop paths fed from it.

# standard SDC — portable across compliant tools
# A clock that passed through a mux output; same rate as master.
create_generated_clock -name clk_mux_out \
-source [get_pins mux_cell/A] -divide_by 1 \
[get_pins mux_cell/Z]

A multiplexer that selects between two different master clocks is a special headache. Each input is a different clock. You may need a generated clock on the mux output for each master, or you use case analysis to fix the select line so only one clock passes. Case analysis sets a constant on a pin, telling the tool one input is always chosen. That removes the ambiguity.

# standard SDC — portable across compliant tools
# Force the mux to select input A for this analysis run.
set_case_analysis 0 [get_pins mux_cell/S]

A worked example: a mux picks between a 4.00 ns clock and a 6.00 ns clock based on a select pin. If you set case analysis so the select is 0 and input A (4.00 ns) wins, the tool times the whole downstream block at 4.00 ns and ignores the 6.00 ns input. You would run a second analysis with the select set to 1 to cover the other mode.

Master-Source Links and Common Errors

The master-source link is the -source pin. It tells the tool where the generated clock's timing comes from. The number one error is pointing it at the wrong pin. If the source pin has no clock reaching it, the generated clock has no master edges to transform, and the tool either errors or silently produces a clock with no meaningful timing. The second common error is defining a generated clock without first defining the master. The master clock must exist and must propagate to the source pin. If you forget the master, the generated clock is an orphan. Always create the master clock first, then the generated clock.

warnings

master

Forgot -invert Wrong capture edge checked Add -invert to match the real circuit wrong capture edge, and a path that fails in silicon looks fine in the report. Match the constraint to the real gate. Finally, watch the divide ratio against the real circuit. If the hardware divides by 4 but you write - divide_by 2 , the generated period is wrong by a factor of two. Every downstream path is then timed against a clock that does not match the silicon. Always read the actual divider logic and set the ratio to match. A practical habit catches most of these traps. After defining all clocks, dump the clock list and study it. Every register should map to exactly one clock. Any register with no clock is a propagation failure. Any register driven by two clocks suggests an overlap that needs a generated clock, case analysis, or grouping to resolve. The few minutes spent reading this list catch generated-clock errors before they reach a long timing run. Watch out, too, for generated clocks that feed other generated clocks. A divider's output may itself be divided again, forming a chain. Each stage must point its -source at the pin one level up, not all the way back to the original master. If you skip a level, the periods still come out right by luck in simple cases but break as soon as a stage adds inversion or an edge shift. Build the chain link by link, and verify each stage's period before adding the next.

Interview Q&A

defined relative to a master clock and inherits its edges, then transforms them. Because the relationship is fixed, the tool times the two as synchronous. A fresh clock has no known relationship to the master, so cross paths cannot be timed correctly.

with -divide_by 2 , point -source at the master, and place the new clock at the divider's output pin. The generated period is 2 × 2.64 = 5.28 ns. Two master edges make one generated edge.

master edges, so you can make odd duty cycles and phase shifts. With a 3.40 ns master, -edges {1 3 5} gives a generated clock that rises at 0, falls at 3.40, and rises again at 6.80, a 6.80 ns period.

through gates without changing rate, but the tool needs to know the gate output carries a clock. Without the definition, downstream paths are mistimed or dropped. The divide-by-1 keeps the same period as the master.

select line so only one clock passes, then run a separate analysis for each mode. For a mux between a 4.00 ns and a 6.00 ns clock, set the select to pick one, time at that rate, then repeat for the other.

generated clock has no master edges. The tool then errors or makes a meaningless clock. Always define the master first and link -source to a pin where the master clock actually arrives.

Key Takeaways

• A generated clock inherits a master clock's edges and transforms them, keeping a fixed, timeable relationship.
• Divide lengthens the period (divide-by-2 of 2.64 ns gives 5.28 ns); multiply shortens it.
• The -edges option builds clocks from chosen master edges for odd duty cycles and phase shifts.
• Combinational generated clocks need -divide_by 1 so the tool recognizes a clock at a gate output.
• The master-source link is critical; a wrong -source pin or a missing master clock is the most common error.