Design-Rule Constraints — Transition, Cap & Fanout

Timing constraints — clocks, generated clocks, I/O delays, exceptions, OCV and MCMM setup

Design-Rule Constraints — Transition, Cap, Fanout (Deep)

Timing is not the only thing a chip must obey. A gate can meet every setup and hold check and still be unbuildable. Its output may swing too slowly. It may drive too much capacitance. It may fan out to too many gates. These are electrical health rules. They are called design-rule constraints. This chapter goes deep on the three main ones: transition, capacitance, and fanout. We keep the format generic. We call it SDC. We never name a tool or product. We say "the synthesis tool" for the engine that builds logic and "the timing tool" for the engine that checks paths.

What a Design Rule Is and Is Not

A design-rule constraint is a ceiling on an electrical quantity. It says "this signal's slew must not exceed X" or "this pin must not drive more than Y capacitance." It is a hard limit on health, not a timing margin. This is the key distinction. A timing path runs from one flop to another and is judged by slack. A design rule judges a single point against a fixed ceiling. The two are independent. A net can have huge positive slack and still break a transition rule. A net can be tight on timing and still pass every design rule. They measure different things.

Why do these rules exist? A slow slew wastes power and can cause logic to glitch. A gate driving too much load may never reach a clean high or low. A gate with too many fanouts is overloaded. The rules keep every node electrically sane regardless of timing.

The Transition Constraint

Transition, also called slew, is the time a signal takes to swing between low and high. A clean design wants slews to stay sharp. The command set_max_transition sets the largest slew any covered pin may have. When the synthesis tool sees a node that would exceed this ceiling, it fixes it. It may insert a buffer. It may upsize the driving gate. The goal is to bring the slew back under the limit. The constraint shapes the netlist even though it says nothing about flop-to-flop timing. You can apply the ceiling to a whole design or to a chosen set of objects. A tighter local limit can protect a sensitive block. A looser global limit can relax the rest.

# standard SDC — portable across compliant tools
# Global slew ceiling, then a tighter ceiling on a sensitive clock-feeding block.
set_max_transition 0.642 [current_design]
set_max_transition 0.318 [get_cells core_pll_buf]

A worked feel. A node has a computed slew of 0.731 ns. The global ceiling is 0.642 ns. The node is over by 0.089 ns. The synthesis tool upsizes the driver, the slew drops to 0.557 ns, and the violation clears. No timing path moved; only the slew was repaired.

The Capacitance Constraint

Capacitance is the electrical load a pin must charge. Too much load makes a gate strain. The command set_max_capacitance sets the largest capacitance a covered pin may drive. It is the loadside cousin of the transition rule.

Transition and capacitance are related but not identical. A gate can pass the capacitance ceiling yet still produce a slow slew, because slew also depends on drive strength. So both rules are checked. A node must satisfy each one independently.

# standard SDC — portable across compliant tools
# Cap the load any output may drive across the design.
set_max_capacitance 0.0935 [current_design]

The Fanout Constraint

Fanout is the number of gate inputs a single driver feeds. A high fanout overloads a gate. The command set_max_fanout sets the largest fanout allowed. When a node exceeds it, the synthesis tool builds a buffer tree to share the load. Fanout is often expressed as a unitless count or as a "fanout load" number that weights each input. The exact unit depends on the library, but the idea is constant: do not let one gate drive too many sinks.

# standard SDC — portable across compliant tools
set_max_fanout 24 [current_design]
set_max_fanout 8  [get_cells secure_key_reg]

A worked feel. A net drives 31 inputs. The ceiling is 24. The synthesis tool inserts two buffers, splitting the load into three branches of roughly 10 each. Every branch now passes, and the original driver sees only the buffers as its load.

Library Limits Versus User Limits, and Priority

The library itself carries built-in ceilings. Each cell has a maximum slew and a maximum capacitance it is characterized for. These are library limits. Beyond them, the cell's timing numbers are not trustworthy. You can also impose your own ceilings with the SDC commands above. These are user limits. The two coexist. The tool honors both, and the tighter one wins for any given node. If the library says a pin may drive 0.110 pF and you set 0.0935 pF, the effective ceiling is 0.0935 pF, because it is stricter.

This priority rule has a practical effect. You can tighten a design with user limits, but you cannot loosen past safe library characterization in any meaningful way, because the library ceiling still guards correctness. Setting a user cap looser than the library does not unlock unsafe behavior; the library limit remains.

# illustrative — names vary by tool
# Review which nodes violate any design rule and by how much.
report_constraint -max_transition -max_capacitance -max_fanout
report_design_rule_violations -sort_by slack

A worked illustration of priority. A pin's library maximum slew is 0.700 ns. You set a user maximum of 0.642 ns. A node computes 0.668 ns. It passes the library rule but breaks the user rule, so it is flagged. The effective ceiling is the tighter 0.642 ns, and the synthesis tool repairs the node to satisfy it.

Interview Q&A

slack between two flops. A design rule judges one point against a fixed electrical ceiling. They measure different things. A net can have large positive slack and still break a slew rule, and a tight net can pass every design rule.

swing time of a signal at covered pins. When a node exceeds the ceiling, the synthesis tool repairs it, usually by inserting a buffer or upsizing the driver, until the slew falls under the limit.

on both load and drive strength, so a gate can stay under the capacitance ceiling and still produce a

slew that exceeds the transition ceiling. The two rules are checked independently and a node must satisfy each.

into branches, each driving a share of the original sinks through inserted buffers. Every branch then meets the fanout ceiling, and the original driver sees only the buffers.

for that node. If your user limit is stricter, it binds; if the library limit is stricter, it binds. The effective ceiling is always the smaller value, which guards both your intent and library correctness.

only tighten the effective ceiling. The library limit remains in force, so loosening a user cap past the library does not unlock unsafe behavior, because the stricter library ceiling still applies.

Key Takeaways

• Design rules cap electrical health, not slack. They guard slew, load, and fanout at single points, independent of flop-to-flop timing.
• Transition and capacitance are distinct. A node can pass one and fail the other, so both are checked separately.
• Fanout violations are fixed with buffer trees. An overloaded driver is split into balanced branches that each meet the ceiling.
• The tighter limit always wins. Between library and user ceilings, the stricter value is the binding constraint for every node.
• User limits only tighten. They cannot loosen past safe library characterization, so the library ceiling always protects correctness.