Clock Generation — PLL & DLL

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

Why a Chip Makes Its Own Clock

A board can only deliver a slow, clean reference clock. Maybe 50 or 100 MHz. But the chip inside wants to run at a few gigahertz. So the chip must take the slow reference and multiply it up. It must also clean up the timing and line up edges. The circuits that do this are the PLL (phase-locked loop) and the DLL (delay-locked loop). This chapter explains both in plain words. They are feedback loops: they compare their output to a reference and keep adjusting until the two line up. Once "locked," they hold that match. The idea is simple. The details are where the skill lies.

The Phase-Locked Loop, Block by Block

A PLL turns a slow reference into a fast, steady output whose edges track the reference. It is a loop of five parts.

• Phase detector: compares the reference edge with a fed-back copy of the output. It reports which is ahead and by how much.
• Charge pump: turns that "ahead/behind" signal into a small push of current, up or down.
• Loop filter: smooths the pushes into a steady control voltage. It sets how fast and how stable the loop is.
• Voltage-controlled oscillator (VCO): makes the output clock. Its speed rises or falls with the control voltage.
• Divider: divides the fast output down before feeding it back, so the loop can compare it to the slow reference.

The divider sets the multiply factor. If the divider divides by 30, the loop forces the output to be 30 times the reference. That is how a 100 MHz reference becomes a 3 GHz clock.

Worked example — the multiply ratio

A board gives a 80 MHz reference. The chip needs a 2.4 GHz clock.

divide ratio N = output / reference = 2400 / 80 = 30
so the feedback divider must divide by 30

Set the divider to 30 and the locked output is 80 MHz × 30 = 2.4 GHz.

How the Loop Locks

At power-up the output is wrong. The phase detector sees a big mismatch. The charge pump pushes the control voltage hard. The VCO speeds up or slows down. Step by step, the fed-back divided clock creeps toward the reference. When they match in both frequency and phase, the pushes stop averaging out and settle. The loop is locked. Lock takes time, called lock time. A fast loop locks quickly but is more jittery and can overshoot. A slow loop is steady but takes longer. The loop filter sets this balance.

Worked example — lock time rough estimate

Suppose a loop settles in about 50 reference cycles, and the reference is 80 MHz (period 12.5 ns).

lock time ≈ 50 × 12.5 ns = 625 ns

Under a microsecond to lock is typical. Systems wait for a "lock" flag before trusting the clock.

The Delay-Locked Loop

A DLL solves a narrower problem. It does not make a new frequency. It takes a clock and lines up its edge with a reference, removing skew. It does this with a chain of adjustable delay elements instead of an oscillator. A phase detector compares the delayed clock to the reference. A control loop tunes the delay chain until the edges align. Because there is no oscillator, a DLL cannot drift or accumulate phase error the way a PLL can. It is simpler and more stable, but it only delays — it cannot multiply frequency on its own.

Jitter — the Enemy

Jitter is small, random wobble in where a clock edge lands. One cycle the edge is a touch early; the next, a touch late. Jitter eats timing margin, because the capture edge might come sooner than expected. Too much jitter and setup checks fail. Jitter comes from several places: noise in the VCO, ripple on the control voltage, supply noise, and noise on the reference itself. Good design fights each: a clean supply, a well-tuned loop filter, and a low-noise VCO.

Worked example — jitter eats margin

A 2.4 GHz clock has a period of about 417 ps. Peak-to-peak jitter is 15 ps.

period = 1 / 2.4e9 ≈ 417 ps
usable window = 417 - 15 ≈ 402 ps
jitter cost ≈ 3.6% of the cycle

Almost 4% of every cycle is lost to jitter before any logic runs. At higher speeds this fraction grows, which is why low jitter is prized.

Putting It Together in a Chip

A real chip often has several of these loops. One main PLL multiplies the board reference up to the core speed. Smaller PLLs or DLLs make special clocks for memory interfaces or high-speed links. DLLs de-skew clocks that must line up tightly across a wide interface. The clock from the PLL then enters the clock tree, which fans it out to every register with low skew. So the PLL makes the fast clock; the tree delivers it. Both must be good for the chip to run fast and reliably.

Interview Q&A

to low hundreds of MHz), but the chip needs gigahertz clocks. A PLL multiplies the slow reference up to the high internal frequency while keeping the edges locked to the reference.

mismatch), charge pump (turns mismatch into a current push), loop filter (smooths it into a steady control voltage and sets stability), VCO (generates the output clock from that voltage), and divider (divides the output down for comparison, setting the multiply ratio).

down output to match the reference, so the output equals the reference times the divider value — e.g. an 80 MHz reference with a divide-by-30 gives 2.4 GHz.

so it only delays or aligns a clock's edge — it cannot create a new frequency. Because it has no oscillator, it does not accumulate phase error, making it simpler and more stable, and it is used mainly for de-skewing and edge alignment.

clock edge lands. It eats timing margin because the capture edge can arrive earlier than expected; at a 417 ps period, 15 ps of jitter already costs nearly 4% of the cycle, and the fraction grows at higher speeds.

the correct frequency and phase after start-up. It is set by the loop filter: a fast loop locks quickly but is

jitterier and can overshoot, while a slow loop is steadier but takes longer; systems wait for a lock flag before trusting the clock.

Key Takeaways

• A PLL multiplies a slow board reference up to gigahertz core clocks using a feedback loop.
• The loop is phase detector → charge pump → loop filter → VCO → divider; the divider sets the multiply ratio.
• A DLL only aligns/de-skews a clock with an adjustable delay line — no new frequency, but more stable.
• Jitter (random edge wobble) eats timing margin and is fought with clean supplies and a good loop filter.
• The PLL makes the fast clock; the clock tree delivers it with low skew — both must be good.