• Smaller data sets give faster run times.
• Blocks can be reused once implemented.
• IP blocks are easier to drop into a hierarchical modular design than into a flat one.

Hierarchical design - disadvantages:

• Preliminary block characterization is inaccurate and can produce false top- and block-level violations or hide real ones.
• Block timing models must be updated frequently when blocks change.
• Detail is hidden or lost because of modeling at the boundaries.

KEY: Flat design gives accurate timing but huge data; hierarchical design enables parallel work and reuse but relies on imperfect block models.

Chip-Level vs Block-Level Design

• Chip design has IO pads, whereas block design has pins.
• Chip design uses all available metal layers; a block may not use all of them.
• A chip is generally rectangular, while blocks can be rectangular or rectilinear.
• Chip design needs packaging, whereas block design ends as a macro.

KEY: Chips have IO pads, use all metals and need packaging; blocks have pins, may use fewer metals and end as macros.

Splitting a Net to Reduce Delay

Consider a net of length L modeled as distributed RC sections, with resistance per unit length Rp and capacitance per unit length Cp.

• The total net resistance is Rt = L x Rp and the total capacitance is Ct = L x Cp, so the total net delay is Dt = Rt x Ct = L^2 x Rp x Cp.
• If you insert a buffer, the net length becomes L/2, so the net delay drops by a factor of about L^2/4.
• Another way to see it: R is proportional to length/area and C is proportional to area/distance, so the RC product is proportional to L^2.