• Across multiple clock domains, behaviour depends on how the clock trees are balanced. If the domains are fully asynchronous, ATPG must mask the receiving flops.

KEY Scan insertion places negedge flops before posedge flops to avoid lockup latches; async domains need ATPG masking.

Scan Chain Reordering - Definition

Answer 1: The tool places standard cells optimally for timing and congestion. In doing so it may detach scan chains and break the ordering created by a scan-insertion tool (such as Synopsys DFT Compiler), then reorder them for optimization while preserving the number of flops in each chain.

Answer 2: During placement, optimization can make a scan chain hard to route because of congestion, so the tool reorders the chain to ease congestion. This can introduce hold-time problems in the chain, sometimes requiring buffers in the scan path. The tool may not keep the chain length exactly the same, and it cannot swap cells across different clock domains.

KEY Scan reordering re-sequences scan cells after placement to cut congestion, keeping flop count but possibly affecting hold.

Congestion

Congestion occurs when the number of routing tracks available in a region is less than the number of tracks required to route it.

KEY Congestion is when required routing tracks exceed the routing tracks available.

Buffer Placement on a Setup Path

Buffers are normally inserted to fix fanout violations, which incidentally relieves setup; otherwise setup is usually fixed by sizing cells. If a buffer must be inserted, place it near the capture path.

Other paths may pass through or originate from the flop near the launch flop, so a buffer there can affect those paths too, improving some and degrading others. Insert the buffer near the launch flop only