Numerical Problems & Worked Solutions

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

How to Use These Problems

These problems train the math behind CMOS design. Each one gives a short statement, then a worked solution you can follow step by step, then a one-line answer. Try to solve each problem on paper first. Then read the worked block to check your method and your numbers. The arithmetic is shown in full so you can spot any step you missed. Work the whole set twice, once for understanding and once for speed.

Problem 1. A gate has an output resistance of 6 kilo-ohm and drives a load capacitance of 12 femtofarad. Estimate the propagation delay using the 0.69 RC model.

Delay = 0.69 * R * C
R = 6 kilo-ohm = 6000 ohm
C = 12 femtofarad = 12e-15 farad
Delay = 0.69 * 6000 * 12e-15
= 0.69 * 7.2e-11
= 4.968e-11 seconds
= 49.7 picoseconds

Answer: About 50 picoseconds. Problem 2. A wire is 1.5 mm long. Its resistance is 0.2 ohm per micron and its capacitance is 0.18 femtofarad per micron. Find the distributed wire delay using 0.38 RC for a distributed line.

Length = 1.5 mm = 1500 micron
R = 0.2 * 1500 = 300 ohm
C = 0.18e-15 * 1500 = 2.7e-13 farad = 270 femtofarad
Delay = 0.38 * R * C
= 0.38 * 300 * 2.7e-13
= 0.38 * 8.1e-11
= 3.078e-11 seconds
= 30.8 picoseconds

Answer: About 31 picoseconds. Problem 3. A long wire of delay 200 ps is split into 4 equal segments with ideal repeaters. Delay scales with the square of segment length. Ignoring buffer delay, find the new total wire delay.

Original delay scales with length squared for one segment.
Split into 4 segments, each is length/4.
Each segment delay = original/16 (since (1/4)^2 = 1/16)
Four segments in series = 4 * (original/16) = original/4
New delay = 200 / 4 = 50 picoseconds

Answer: About 50 picoseconds. Problem 4. An inverter drives a fan-out of 5 identical inverters. Its intrinsic delay is 8 ps and each unit of fan-out adds 4 ps. Find total delay.

Total = intrinsic + (fanout * per-load delay)
= 8 + (5 * 4)
= 8 + 20
= 28 picoseconds

Answer: 28 picoseconds.

Power

Problem 5. A block has 40 fF switched capacitance, runs at 1.2 GHz, on a 0.9 V supply, with activity factor 0.25. Find dynamic power.

P = alpha * C * V^2 * f
alpha = 0.25
C = 40e-15 farad
V^2 = 0.9 * 0.9 = 0.81
f = 1.2e9 hertz
P = 0.25 * 40e-15 * 0.81 * 1.2e9
= 0.25 * 40e-15 * 0.972e9
= 0.25 * 3.888e-5
= 9.72e-6 watt
= 9.72 microwatts

Answer: About 9.7 microwatts. Problem 6. A chip burns 5 W dynamic at 1.0 V. The supply drops to 0.8 V at the same frequency and activity. Find the new dynamic power.

Dynamic power scales with V^2.
Ratio = (0.8 / 1.0)^2 = 0.64
New power = 5 * 0.64 = 3.2 watts

Answer: 3.2 watts. Problem 7. A transistor has off-current of 20 nA per micron and total off width of 5000 micron at 0.9 V. Find the leakage power.

Total leakage current = 20e-9 * 5000 = 1e-4 ampere = 100 microampere
P = I * V = 1e-4 * 0.9 = 9e-5 watt = 90 microwatts

Answer: 90 microwatts. Problem 8. A design has 6 W dynamic and 2 W leakage. Find the leakage fraction of total power.

Total = 6 + 2 = 8 watts
Leakage fraction = 2 / 8 = 0.25 = 25 percent

Answer: 25 percent. Problem 9. Clock gating removes switching on a clock net that contributed 1.5 W out of 8 W total. Find the new total power and the percent saved.

New total = 8 - 1.5 = 6.5 watts
Percent saved = 1.5 / 8 = 0.1875 = 18.75 percent

Answer: 6.5 watts, about 18.8 percent saved.

Sizing & Logical Effort

Problem 10. A 2-input NAND has logical effort 4/3 and drives an electrical effort (load over input) of 6. Find its stage effort.

Stage effort = logical effort * electrical effort
= (4/3) * 6
= 8

Answer: 8. Problem 11. A path of inverters must drive a total electrical effort of 64. The ideal stage effort is 4. Find the number of stages.

Stages N satisfies (stage effort)^N = total effort
4^N = 64
N = log(64) / log(4) = 1.806 / 0.602 = 3

Answer: 3 stages. Problem 12. A path has total path effort F of 200. Find the best stage effort and stage count, given ideal per-stage effort near 4.

N = round( ln(F) / ln(4) )
ln(200) = 5.298
ln(4) = 1.386
N = 5.298 / 1.386 = 3.82, round to 4 stages
Per-stage effort = F^(1/N) = 200^(0.25)
200^0.25 = (200^0.5)^0.5 = 14.14^0.5 = 3.76

Answer: 4 stages, each with effort about 3.76. Problem 13. An inverter has input capacitance 3 fF. To drive a 48 fF load at stage effort 4, find the needed sizing chain ratio per stage and stage count.

Electrical effort = 48 / 3 = 16
Stages: 4^N = 16, so N = 2
Each stage scales up by factor 4.
Stage 1 input = 3 fF, stage 2 input = 12 fF, load = 48 fF

Answer: 2 stages, each scaled by 4x. Problem 14. A 2-input NOR has logical effort 5/3. Compare its delay driving effort 9 to a 2-input NAND (logical effort 4/3) at the same load.

NOR stage effort = (5/3) * 9 = 15
NAND stage effort = (4/3) * 9 = 12
Difference = 15 - 12 = 3
NOR is slower by ratio 15/12 = 1.25, or 25 percent

Answer: NOR is about 25 percent slower.

Interconnect

Problem 15. A power rail carries 80 mA through a resistance of 0.5 ohm. Find the IR drop and its percent of a 1.0 V supply.

IR drop = I * R = 0.08 * 0.5 = 0.04 volt = 40 millivolt
Percent of supply = 0.04 / 1.0 = 4 percent

Answer: 40 mV, which is 4 percent. Problem 16. A via has resistance 5 ohm. Eight identical vias are placed in parallel. Find the combined resistance.

Parallel resistance = single via R / number of vias
= 5 / 8 = 0.625 ohm

Answer: 0.625 ohm.

Problem 17. A wire carries 1.2 mA and has a cross-section of 0.3 square micron. Find current density and compare to a 2 mA per square micron limit.

Current density = current / area
= 1.2e-3 / 0.3 = 4e-3 ampere per square micron = 4 mA per square micron
Limit = 2 mA per square micron
4 > 2, so it exceeds the limit by 2x

Answer: 4 mA per square micron, twice the safe limit. Problem 18. Two parallel wires have coupling capacitance 8 fF. An aggressor swings 1.0 V in 30 ps. Estimate the coupled charge and peak coupling current.

Charge = C * V = 8e-15 * 1.0 = 8e-15 coulomb
Peak current = charge / time = 8e-15 / 30e-12
= 2.67e-4 ampere = 267 microampere

Answer: 8 fC of charge, about 267 microamperes peak.

Memory & Arrays

Problem 19. An SRAM array has 256 rows and 128 columns. Find the total number of bits and the number of 6T cell transistors.

Bits = rows * columns = 256 * 128 = 32768 bits = 32 kilobits
Transistors = bits * 6 = 32768 * 6 = 196608 transistors

Answer: 32768 bits and 196608 transistors. Problem 20. A DRAM cell holds 25 fF and must keep at least 0.4 V. Leakage current is 1 fA. Find the maximum retention time before it drops 0.5 V.

Time = C * delta-V / I
= 25e-15 * 0.5 / 1e-15
= 1.25e-14 / 1e-15
= 12.5 seconds

Answer: About 12.5 seconds. Problem 21. A bit line has 200 fF capacitance. A cell dumps 20 fF of charge at 0.9 V onto it. Find the bit-line voltage change before sense amplification.

Charge from cell = C_cell * V = 20e-15 * 0.9 = 1.8e-14 coulomb
Voltage change = charge / bitline C = 1.8e-14 / 200e-15
= 0.09 volt = 90 millivolt

Answer: About 90 millivolts. Problem 22. A memory of 1 megabit refreshes every cell within 64 ms, one row at a time, with 1024 rows. Find the time budget per row refresh.

Time per row = refresh window / number of rows
= 64e-3 / 1024
= 6.25e-5 seconds
= 62.5 microseconds

Answer: 62.5 microseconds per row.

Scaling

Problem 23. A process scales linear dimensions by 0.7 (constant-field scaling). Find the change in transistor area and the area for the same logic.

Area scales with length * width = 0.7 * 0.7 = 0.49
New area = 49 percent of old, about half

Answer: Area drops to about 49 percent. Problem 24. Under ideal constant-field scaling with factor 0.7, delay scales by the same factor. A gate was 20 ps. Find the new delay and the speed gain.

New delay = 20 * 0.7 = 14 picoseconds
Speed gain = old / new = 20 / 14 = 1.43, about 43 percent faster

Answer: 14 picoseconds, about 43 percent faster. Problem 25. Under ideal constant-field scaling with factor k = 0.7, dynamic power per gate scales with k cubed. A gate burned 10 microwatts. Find the new power.

Power scaling = k^3 = 0.7^3 = 0.343
New power = 10 * 0.343 = 3.43 microwatts

Answer: About 3.4 microwatts. Problem 26. A chip moves from 2 metal mask layers needing rework to a node with 30 percent higher fab cost but 2x more transistors per area. Find the cost per transistor change relative to before.

Cost per area rises by factor 1.3
Transistors per area rises by factor 2
Cost per transistor = 1.3 / 2 = 0.65
That is 65 percent of the old cost, a 35 percent reduction

Answer: Cost per transistor falls to about 65 percent, a 35 percent reduction.

Problem 27. A design has FO4 delay of 16 ps and a critical path of 22 FO4 delays. Find the maximum clock frequency.

Path delay = 22 * 16 ps = 352 ps = 3.52e-10 seconds
Max frequency = 1 / path delay = 1 / 3.52e-10
= 2.84e9 hertz = 2.84 GHz

Answer: About 2.84 GHz.