Routing, Vias & Design Rules

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

Connecting a Million Things

After cells are placed, they must be wired together. This is routing: drawing the metal connections that carry every signal. A big chip has millions of wires on many stacked metal layers. Routing them all without crossings, shorts, or rule violations is one of the hardest steps in chip design. This chapter explains routing in plain words: the metal stack, how wires change layers through vias, the difference between global and detailed routing, design rules, and special nets like clocks and power.

The Metal Stack

A chip wires signals on many layers of metal, stacked above the transistors. Lower layers are thin and used for short, local connections. Upper layers are thick and used for long wires and power, because thicker metal has less resistance. Wires on one layer run mostly in one direction; the next layer runs the other way. This alternating pattern lets wires cross by simply using different layers. To go from one layer to another, a wire uses a via: a small vertical metal plug between layers.

Worked example — layers and direction

A signal must go right then up. Horizontal wires run on layer 2, vertical on layer 3.

segment 1 (rightward): layer 2
via from layer 2 to layer 3
segment 2 (upward):    layer 3

The via is what lets the wire turn by switching layers. Every bend or crossing uses one.

Vias and Their Cost

A via connects two layers, but it is not free. A via adds resistance and can fail more easily than plain wire, because it is a small, stressed structure. Too many vias on a path slow it down and lower reliability. So routers try to keep important nets on few layers with few vias, or use doubled vias (two side by side) for reliability on critical connections. Counting and managing vias is part of good routing.

Worked example — via resistance adds up

A net crosses 6 vias, each 4 ohms, plus 30 ohms of wire.

via resistance = 6 × 4 = 24 Ω
total = 30 + 24 = 54 Ω
vias added 24/54 ≈ 44% of the net's resistance

Nearly half the net's resistance came from vias. On a critical net, the router would reduce via count or double them up.

Global Then Detailed Routing

Routing happens in two passes. Global routing plans the rough path: it divides the chip into a coarse grid and decides which regions each wire passes through, balancing demand so no region overflows. It does not draw exact wires yet. Detailed routing then draws the actual metal: exact tracks, exact vias, obeying every spacing rule. It fills in the plan global routing made. Splitting the job this way makes a huge problem manageable — plan coarsely, then commit precisely.

Design Rules

Manufacturing cannot make shapes perfectly. So there are design rules: minimum widths, minimum spacings, and overlap requirements that guarantee the chip can actually be built. Every wire and via must obey them. Examples: a wire must be at least a minimum width or it may break; two wires must be at least a minimum distance apart or they may short; a via must be fully covered by metal or it may not connect. The router enforces thousands of such rules. A design-rule check (DRC) at the end confirms none are broken.

Worked example — spacing check

Minimum spacing is 0.05 µm. Two wires are drawn 0.04 µm apart.

0.04 µm < 0.05 µm → spacing violation
the router must move one wire to ≥ 0.05 µm

A single violation can ruin a chip, so the router fixes every one before sign-off.

Special Nets

Some nets get special treatment because they matter more. Clock nets must reach every register with low skew, so they are routed early on good layers with careful balancing (clock tree synthesis). Power nets need wide metal and a strong mesh to carry large currents with low IR drop. Sensitive signals may get shielding (ground wires on each side) to block crosstalk. Long buses may use wider wires on thick layers to stay fast.

Worked example — shielding cost

A 32-bit bus is shielded with a ground wire between each pair.

signal wires = 32
shield wires ≈ 33
total tracks ≈ 65 (about double)

Shielding roughly doubles the track count for that bus. It is worth it only for the most sensitive nets, which is why it is used sparingly.

Interview Q&A

for millions of wires, with thin lower layers for short local connections and thick upper layers for long wires and power (less resistance). Alternating the wiring direction per layer lets wires cross simply by using different layers.

adjacent layers, used whenever a wire changes layer (e.g. to turn). It adds resistance and is more failure-prone than plain wire, so routers limit via count on important nets or double vias for reliability.

it decides which regions each wire passes through and balances congestion, without drawing exact metal. Detailed routing then draws the actual tracks and vias obeying every spacing rule, filling in the global plan; splitting the job makes a massive problem manageable.

overlap requirements that guarantee the chip can actually be manufactured despite imperfect fabrication. A too-thin wire may break, too-close wires may short, and an under-enclosed via may not connect, so the router enforces thousands of them and a DRC confirms none are broken.

and carefully balanced for low skew (clock tree synthesis). Power nets use wide metal in a strong mesh with many vias to carry large currents with low IR drop, because both reliability and timing depend on them.

sensitive signal to block crosstalk from neighbours. It roughly doubles the track count for that net, so it is reserved for the most sensitive signals like critical clocks or analog lines.

Key Takeaways

• Chips wire signals on a stack of metal layers with alternating directions; vias connect layers.
• Vias add resistance and risk — routers minimise or double them on critical nets.
• Routing runs global (coarse plan) then detailed (exact metal) to tame a massive problem.
• Design rules (width, spacing, enclosure) ensure manufacturability; a final DRC must be clean.
• Clocks, power, and sensitive nets get special routing — early balancing, wide meshes, and shielding.