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VLSI Physical Design  ›  Ch 3. Placement & Congestion

KEY Placement inputs: a completed floorplan, the SDC/MMMC, and design targets like max_trans and max_area.

Results Produced by Placement

  • A legalised cell placement.
  • A congestion picture.
  • A design density picture.

KEY Placement produces legalised cell placement plus congestion and density results.

Constraints Used During Placement

  • Placement blockages - partial, soft and hard.
  • Bounds - guide, region and fence.
  • Magnet placement.
  • Relative placement.
  • Keepout margin and cell padding.

KEY Placement constraints include blockages, bounds, magnet and relative placement, and keepout/padding.

Checks Performed at Placement

  • Legality of the cell placement and the resulting timing.
  • Module placement - whether each module is kept together.
  • Path-by-path congestion review.
  • Congestion, defined as required tracks divided by available tracks.
  • Required tracks can be reduced by lowering cell density and pin density and by avoiding criss-cross signal routing caused by wrongly placed cells on a path.
  • Cell density is managed with soft, partial and hard blockages and with guide, region, fence and keepout-margin constraints.
  • Pin density is also checked - case 1: pin density high but cell density acceptable; case 2: pin density acceptable but cell density high; case 3: both pin and cell density high.