Low-Power Design Techniques

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

Power Is the Real Limit

For years, speed was the goal. Now power is. A chip that runs hot must be slowed down, cooled, or shut off in parts. A battery chip that drains fast is useless. So low-power design is not an extra step. It runs through every choice, from the transistor up to the system. This chapter gathers the main low-power techniques in one place, in plain words. Each one attacks a different part of the power bill. Used together, they can cut power many times over.

Where Power Goes

There are two big buckets. Dynamic power is burned when signals switch. Static power (leakage) is burned all the time, even when nothing switches, because tiny transistors never fully turn off. Dynamic power follows a simple shape: it grows with how often things switch, with the load being driven, and with the square of the voltage. Static power grows with how many transistors there are and gets much worse as they shrink and as the chip heats up.

Worked example — the voltage-squared lever

Dynamic power scales with voltage squared. Drop the supply from 1.0 V to 0.8 V.

ratio = (0.8 / 1.0)² = 0.64
power falls to 64% → a 36% saving

A small voltage cut gives a big power cut. This is why voltage scaling is the strongest single lever. The catch: lower voltage makes gates slower, so it is used where speed is not critical.

Clock Gating

The clock network is one of the busiest, most power-hungry nets on a chip. It toggles every cycle, everywhere. But many registers do not need a new value every cycle. Feeding them the clock anyway wastes power. Clock gating turns off the clock to a block when it is idle. A small gating cell holds the clock steady when an enable signal says "nothing to do here." No toggling means no dynamic power in that block's clock and registers.

A good integrated clock-gating cell latches the enable so the gated clock never glitches (makes a runt pulse). Synthesis tools insert these automatically when they see registers that reload only under a condition.

Worked example — clock-gating saving

A register bank's clock and flops burn 20 mW when clocked every cycle. It is actually busy only 30% of the time.

gated power ≈ 20 mW × 0.30 = 6 mW
saving = 20 - 6 = 14 mW (70% of that block's clock power)

Power Gating

Clock gating stops switching but the block still leaks. Power gating goes further: it cuts the supply to a block entirely. A large switch transistor (a sleep transistor) sits between the real supply and the block's local supply. Turn it off and the block draws almost no power at all. This kills leakage, which matters most for blocks that sit idle for long times. The cost is wake-up time and complexity. You must save any needed state before sleeping, because the block loses its values when powered down.

Retention registers solve the state problem. They keep a tiny always-on cell that holds the value while the main logic sleeps. On wake-up, the value is restored.

Multi-Vt: Mixing Fast and Slow Transistors

Transistors can be built with different threshold voltages (Vt — the gate voltage at which they turn on). A low-Vt device is fast but leaks a lot. A high-Vt device is slow but leaks little. A library usually offers several flavours. The trick is to use fast, leaky cells only on the few paths that need the speed. Everywhere else, use slow, low-leakage cells. Most paths in a design have timing slack to spare, so most cells can be the low-leakage kind.

Worked example — multi-Vt leakage saving

A block has 100,000 cells. If all are low-Vt, each leaks 50 nA. Only 8% of cells sit on critical paths.

all low-Vt:  100000 × 50 nA = 5.0 mA leakage
mixed: 8000 × 50 nA + 92000 × 8 nA
= 0.40 mA + 0.74 mA = 1.14 mA
saving ≈ 77% of leakage

You keep nearly all the speed but cut most of the leakage. This is one of the easiest, highest-value low-power moves.

Voltage and Frequency Scaling

Dynamic voltage and frequency scaling (DVFS) changes the supply and clock speed on the fly to match the work. When demand is high, run fast at full voltage. When demand is low, drop both. Because power scales with voltage squared and with frequency, slowing down a little saves a lot.

The system needs a way to sense load and a controller to pick the operating point. It also needs the voltage source to change cleanly without crashing the logic.

Multiple Voltage Domains

Different blocks have different needs. A processor core may need high voltage for speed. A background block may run fine at low voltage. So a chip can split into several voltage domains, each at its own supply. Signals crossing between domains need level shifters (to fix the voltage gap) and, near power gating, isolation cells (to hold a clean value when a neighbour domain is off). Getting these boundary cells right is the tricky part of multi-domain design. Miss one and a floating signal can corrupt a powered block.

Interview Q&A

signals switch and grows with activity, load, and the square of voltage. Leakage (static) power is burned all the time because tiny transistors never fully turn off; it grows with device count, lower threshold voltage, and temperature.

squared, so even a small cut gives a large saving — dropping from 1.0 V to 0.8 V cuts dynamic power to about 64%. The trade-off is that lower voltage makes gates slower, so it is applied where speed allows.

to an idle block, removing its dynamic power while keeping state, but the block still leaks. Power gating cuts the supply entirely, removing leakage too, but the block loses its state unless retention cells are used and it needs wake-up time.

only on the few timing-critical paths, and slow low-leakage high-Vt cells everywhere else. Since most paths have slack, most cells can be low-leakage, cutting leakage greatly while keeping the critical paths fast.

both supply voltage and clock speed when the workload is light. Because power scales with voltage squared and with frequency, easing off a little saves a large amount of power, while full settings return when demand rises.

gap on signals crossing domains; isolation cells clamp a signal to a safe value when its source domain is powered off; retention registers hold state through a power-down. Missing one can let a floating signal corrupt a powered block.

Key Takeaways

• Power splits into dynamic (switching) and leakage (always-on); modern design must attack both.
• Voltage is the biggest lever because dynamic power scales with voltage squared.
• Clock gating removes idle switching; power gating removes leakage but needs retention to keep state.
• Multi-Vt uses fast cells only on critical paths and low-leakage cells elsewhere — big leakage cuts, little speed loss.
• DVFS and multiple voltage domains match power to the work, but need careful level-shifter and isolation boundary cells.