Tighter Transition on Clock vs Data

• It reduces crosstalk on the clock.
• It gives better skew control.
• It causes less short-circuit current.

KEY: A sharper clock transition gives less crosstalk, better skew and lower short-circuit current.

How Buffer Insertion Is Done

• Automatically with insert_buffer, or manually using connect/disconnect.

TCL-based reuse - bypass an existing buffer BUF1 from one path and use it in the required path (driving AND1/a): Step 1 - disconnect the net on BUF1/a. Step 2 - disconnect the pin from the net on BUF1/z. Step 3 - connect the net that was on BUF1/a to the pins previously driven by BUF1/z. Step 4 - disconnect AND1/a from its net. Step 5 - connect the net that was on AND1/a to BUF1/a. Step 6 - connect the net of BUF1/z to AND1/a.

KEY: Buffers are inserted automatically (insert_buffer), manually, or by TCL-reusing an existing buffer between paths.

Ideal Clock Characteristics for Timing

• The clock should be free of glitches.
• Its period should be properly defined, with proper phase relationships established between different clocks of interest.
• It must meet the pulse-width requirements.
• Jitter must be accounted for as clock speeds rise - for example, a PLL has a maximum jitter spec.
• When data is transferred from one clock edge to another, the worst-case duty cycle should be used.

KEY: An ideal clock is glitch-free, well-defined in period/phase, meets pulse width, and accounts for jitter.