44 CMOS VLSI Design

Interview Q&A Bank — Physical & Systems

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

How to Use This Bank

This bank covers the physical and system side of CMOS chips. That means wires, layout, memory, clocks, low power, test, and the overall design flow. Read each question, try your own short answer, then check it. Keep replies to two or three sentences. Many answers include a number, since interviewers want concrete reasoning, not vague talk. Repeat the set until the facts come fast.

What is interconnect in a chip? Interconnect is the network of metal wires that carry signals and

power between transistors. It is built in stacked metal layers above the silicon. Modern chips can have 12 or more metal layers.

Why does wire delay matter more in advanced nodes? As transistors shrink, gates get faster

but wires do not scale as well. Wire resistance per length rises sharply as wires get thin. So interconnect delay can dominate, sometimes over half of total path delay.

What is the RC delay of a wire? A wire's delay grows with the product of its resistance and

capacitance, both proportional to length. So delay rises with the square of length. A 1 mm wire might add hundreds of picoseconds without help.

What is a repeater or buffer insertion? A repeater is a buffer placed in a long wire to break it

into shorter segments. Since delay grows with length squared, splitting a wire cuts total delay. Repeaters can lower long-wire delay by 2x or more.

What is crosstalk? Crosstalk is unwanted coupling between neighboring wires through their

mutual capacitance. A switching aggressor can inject a glitch or shift the timing of a victim line. Spacing and shielding reduce it.

What is electromigration? Electromigration is the slow movement of metal atoms caused by

high current density over time. It can open or short a wire after years of use. Designers cap current density, often near a few mA per square micron.

What is IR drop? IR drop is the voltage lost across the resistance of power wires. It lowers the

supply seen by far cells and slows them. A healthy budget keeps IR drop under about 5 percent of the supply.

Why are wider metal layers used for power and clocks? Wider, thicker upper metals have

lower resistance, which cuts IR drop and clock skew. Signals on lower layers stay thin and dense. So power and clock distribution use the top layers.

What is the difference between local and global interconnect? Local interconnect is thin,

short, and dense, linking nearby cells. Global interconnect is wide and long, spanning the chip on upper layers. Global wires carry clocks, buses, and power.

What is a via? A via is a small vertical metal plug connecting two stacked metal layers. Each via

has resistance, so designers often use multiple vias in parallel. This lowers resistance and improves reliability.

Layout & Fabrication

What are design rules? Design rules are the minimum spacing and width limits that the factory

can build reliably. They prevent shorts and broken shapes. Violating them risks yield loss or a nonworking chip.

What is photolithography? Photolithography prints circuit patterns onto the wafer using light

through a mask. Each layer needs its own mask and exposure step. Feature sizes have shrunk far below the wavelength of the light used.

What is a standard cell? A standard cell is a pre-designed logic gate with a fixed height and

known timing. Cells line up in rows that share power rails. This makes automated place-and-route possible.

What is the well in CMOS layout? A well is a doped region that hosts transistors of the opposite

type. NMOS sits in a p-substrate and PMOS sits in an n-well. Wells must be tied to the proper supply to avoid latch-up.

What is latch-up? Latch-up is an unwanted low-resistance path between supply and ground

through parasitic bipolar devices. It can destroy the chip with high current. Well and substrate taps plus guard rings prevent it.

What is a guard ring? A guard ring is a ring of substrate or well contacts around sensitive

devices. It collects stray carriers and ties the body firmly to a supply. It guards against latch-up and noise.

What is antenna effect? The antenna effect is charge buildup on a metal during fabrication that

can damage a thin gate oxide. Long metals connected only to a gate are at risk. A small diode added to the net drains the charge.

What is chemical-mechanical polishing? Chemical-mechanical polishing, or CMP, flattens

each layer before the next is built. A flat surface keeps later lithography in focus. Dummy fill shapes are added to keep density even for CMP.

What is dummy fill? Dummy fill is non-functional metal or poly added to empty areas. It keeps

layer density uniform so CMP and etch behave evenly. It improves yield but adds parasitic capacitance.

What is yield? Yield is the fraction of chips on a wafer that work correctly. It depends on defect

density and chip area. A mature process may yield 80 to 90 percent on a modest die.

Memory

What is an SRAM cell? An SRAM cell stores one bit using two cross-coupled inverters plus

access transistors. The common design uses six transistors, called a 6T cell. It holds data as long as power is on.

What is DRAM? DRAM stores each bit as charge on a tiny capacitor with one access transistor,

a 1T1C cell. The charge leaks, so it must be refreshed periodically, often every 64 milliseconds. It is denser but slower than SRAM.

Why does DRAM need refresh? The storage capacitor slowly leaks its charge through the

access transistor and junctions. Without refresh the stored bit would fade. A refresh reads and rewrites every cell within the retention window.

What is a bit line and a word line? A word line selects a row of cells by turning on their access

transistors. A bit line carries the data into or out of the selected cell. Their crossing defines a single memory cell.

What is a sense amplifier? A sense amplifier detects the tiny voltage difference on the bit lines

and boosts it to a full logic level. It speeds reads and restores the cell value. DRAM reads are destructive, so the amplifier also rewrites.

What is read stability in SRAM? Read stability is the cell's ability to keep its bit while being

read. During a read the access transistors disturb the internal nodes. The static noise margin during read must stay positive, often above 100 mV.

What is the cell ratio in SRAM? The cell ratio compares the strength of the driver transistor to

the access transistor. A higher ratio improves read stability. A common value is about 1.5 to 2.

What is a non-volatile memory? Non-volatile memory keeps its data after power is removed.

Flash memory stores charge on a floating gate. It is used for code and persistent storage.

Why is SRAM used for cache? SRAM is fast and needs no refresh, so it suits the speed-critical

cache near the processor. Access times can be under a nanosecond. The cost is large area, six transistors per bit.

What limits SRAM scaling? As cells shrink, transistor mismatch grows and the noise margins

shrink. Variation makes small cells unreliable. This is why SRAM area scales more slowly than logic.

Clocking

What is clock skew? Clock skew is the difference in clock arrival time between two points. It

can steal or add to timing margin. Designers aim to keep skew under about 5 percent of the clock period.

What is clock jitter? Clock jitter is the cycle-to-cycle variation in the clock edge timing. It comes

from supply noise and the clock source. It eats into the timing budget like skew.

What is a clock tree? A clock tree is the branching network that delivers the clock to all flip-

flops. It is balanced so edges arrive together. An H-tree is one common balanced shape.

What is clock gating? Clock gating shuts off the clock to idle logic to stop needless switching.

Since the clock is a high-activity net, this saves dynamic power. It can cut clock power by 20 to 40 percent.

What is the setup timing equation? The clock period must cover clock-to-Q delay, logic delay,

and setup time, minus useful skew. In short, period is at least Tcq plus Tlogic plus Tsetup. If the period is too small, the path fails setup.

What is the hold timing equation? The earliest data must not arrive before hold time after the

edge. So Tcq plus the shortest logic delay must exceed the hold time plus skew. Hold failures cannot be fixed by slowing the clock.

How do you fix a hold violation? Add delay buffers on the fast path so data arrives later.

Balancing skew also helps. Unlike setup, slowing the clock does not fix hold.

What is a PLL? A PLL, or phase-locked loop, generates a stable high-frequency clock from a

slower reference. It multiplies the reference frequency and locks the phase. It is the heart of on-chip clock generation.

Low Power

What are the main sources of chip power? The two main sources are dynamic switching

power and static leakage power. Dynamic comes from charging capacitance, leakage from off transistors. Short-circuit current adds a small third part.

What is a voltage island? A voltage island is a region of the chip run at its own supply voltage.

Slower blocks run at a lower voltage to save power. Level shifters bridge signals between islands.

What is a level shifter? A level shifter converts a signal from one supply voltage to another. It is

needed when signals cross between voltage islands. Without it, a low-voltage high may not register correctly.

What is back biasing? Back biasing applies a voltage to the transistor body to shift its

threshold. Reverse bias raises Vt to cut leakage; forward bias lowers Vt for speed. It is a runtime power-versus-speed knob.

What is the energy-delay product? The energy-delay product combines energy per operation

and delay into one metric. A lower product means a better balance of speed and efficiency. It helps compare design choices fairly.

Test & Reliability

What is scan testing? Scan testing chains flip-flops into a shift register so test patterns can be

loaded and results read out. It makes internal nodes controllable and observable. It greatly raises fault coverage, often above 95 percent.

What is a stuck-at fault? A stuck-at fault models a node frozen at logic 0 or logic 1. It is the

classic fault model for digital test. Test patterns aim to detect a high percentage of these faults.

What is built-in self-test? Built-in self-test, or BIST, puts pattern generators and checkers on

the chip itself. The chip can test parts of itself without big external testers. It is common for memories.

What is burn-in? Burn-in runs chips at high voltage and temperature to force early failures

before shipping. Weak parts fail in the factory, not in the field. It screens out infant mortality defects.

What is NBTI? NBTI, or Negative Bias Temperature Instability, slowly raises PMOS threshold

under stress over time. It makes circuits slower as they age. Designers add timing margin to cover this aging.

What is ESD protection? ESD protection shields gate oxides from electrostatic discharge

spikes at the pins. Clamp diodes route the surge safely to the rails. A design may target survival of a 2 kV human-body model pulse.

Design Flow

What are the main steps of the digital design flow? The flow goes from RTL description to

logic synthesis, then place-and-route, then timing closure and verification, then tape-out. Each step adds physical detail. Sign-off checks confirm timing, power, and rule compliance before manufacturing.

← Previous Next →