Chapter 5

Clock Tree Synthesis & Skew

Buffers in the Clock Tree

Buffers balance skew - they equalise the flop-to-flop clock delay across the tree.

KEY Clock buffers balance skew across all flops.

No Hold Check Before CTS

Before CTS the clock is ideal - it reaches every flop at the same time, so there is no real skew or transition data. That is still enough for setup analysis, which depends mainly on the data-path delay. Skew, insertion delay and the clock-tree hierarchy only exist after CTS builds the real tree, so hold violations can only be analysed and fixed once CTS is done.

KEY Pre-CTS the clock is ideal - no skew exists, so hold can't be checked until after CTS.

Insertion Delay

Insertion delay appears during clock tree synthesis. CTS builds the clock from the source toward all the sinks (flops). Once the tree is built, the clock signal travels from the source to each sink, and the time it takes is the insertion delay. Along the way CTS adds logic to balance the arrival times at all sinks - this is skew balancing, the main aim of CTS. For more depth, this links closely to the concept of clock latency.

KEY Insertion delay = time for the clock to travel from source to sinks after CTS builds the tree.

Why Routing Waits for CTS

Routing should only start once all data and clock nets are balanced and properly synthesised, and all cells are placed at legal sites - which happens post-placement. But placement alone is not enough; high-fanout