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VLSI Physical Design  ›  Ch 2. Floorplanning & Die

{place_opt.initial_drc.global_route_based 1}.

  • Enable the two-pass flow for place_opt so a better initial placement is produced: set_app_options -list {place_opt.initial_place.two_pass true}.
  • Allow global routing during the initial CTS so congestion is estimated more accurately and the clock tree is built congestion-aware: set_app_options -list {cts.compile.enable_global_route true}.

Note: the first two settings should only be applied when the Synopsys Physical Guidance (SPG) flow is not being used.

KEY For fragmented floorplans, enable GR-based HFS, two-pass placement and GR-aware CTS (skip first two if using SPG).

Reading the Netlist at Floorplan

  • Identify the macros present in the netlist.
  • Cluster the macros according to the logical hierarchy.
  • Space the macros based on their pin counts.
  • Ensure VDD/VSS connections are arranged between the macros.
  • Place soft blockages in macro channels so standard-cell flops are kept out.
  • Add a density screen wherever it is needed.

KEY While floorplanning, find macros, group by hierarchy, space by pin count, handle power and add blockages/screens.

Fixing Transition on a Net Over a Macro

  • Promote the net to a higher metal layer.
  • Increase the driver's strength.
  • Downsize the sink cells.
  • Split the load.
  • Delete nets around the violating net that have positive setup/hold and slew margin, then re-run global route to find alternative paths around the macro and buffer accordingly.

KEY Fix transition over a macro with layer promotion, driver upsizing, sink downsizing, load splitting or local re-route.