Chapter 1
PD Flow & Fundamentals
Sanity Checks on the Netlist
Sanity checks confirm the netlist is healthy from a timing point of view before implementation begins. They also flag problems in library files, constraints, IOs and optimization directives.
Typical netlist issues caught: floating pins, unconstrained pins, undriven input ports, unloaded output ports, pin-direction mismatches and multiple drivers.
They also catch tie-high/tie-low and power pins that are unconnected or wrongly connected, since tie connectivity must always go through tie cells.
KEY: Sanity checks verify netlist, libraries, constraints and IOs are clean before PnR starts.
Flat vs Hierarchical Implementation
Flat implementation:
- Suited to small and medium ASICs.
- Better area usage, since no reserved power/ground space is needed around each sub-block.
Hierarchical implementation:
- Used for very large designs.
- Applied when sub-systems are built independently.
- Only possible when a clear design hierarchy exists.
KEY: Flat - small/medium designs, best area. Hierarchical - very large designs built block by block.
Spotting a Max-Cap Violation
Run report_timing with the -all_violators option (or the equivalent max-cap report); it lists the nets exceeding their maximum capacitance limit.
KEY:
report_timing -all_violatorslists max-cap violations.