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VLSI Physical Design  ›  Ch 2. Floorplanning & Die

Deciding the Core Area

  • Core size is derived from the standard-cell area plus the macro area and their halos.
  • Die size = core size + IO-to-core clearance + pad area (including the IO pitch area) + bond-pad area.
  • The IO-to-core clearance is the gap from the core boundary to the inner edge of the IO pads (the design boundary).

Diagram 0

KEY Core area = cell + macro + halo area; die area adds IO-to-core clearance and pad area.

Utilization and Aspect Ratio

Utilization: a common assumption is that standard cells take about 70% of the base layers, leaving roughly 30% for routing. If the macro area is large, utilization can be raised accordingly.

  • Blockages, macros and pads are all included in the denominator when computing effective utilization.
  • Effective utilization assumes all standard cells - including buffers - sit outside the blockage areas.
  • Aspect ratio: in a five-layer design where layers 1, 3, 5 are horizontal and 2, 4 are vertical, layer 1 is occupied by cell geometry and is unusable for routing. Vias from metal2 to metal1 obstruct about 20% of metal2's vertical routing, so the horizontal-to-vertical