between the N-well and the p-substrate, and gate tunneling leakage current. KEY Dynamic power = short-circuit + external + internal switching; static power = sub-threshold, junction and gate-tunneling leakage.

Reducing Dynamic Power

• Use multi-supply voltage, or simply lower the supply voltage.
• Use multiple frequencies or DVFS, or reduce the operating frequency.
• Lower the switching activity on the nets.
• Cut load and wire capacitance by keeping net lengths short.
• Use place.coarse.icg_auto_bound so registers are placed close to their driving ICG, improving net transitions.
• Add decoupling capacitors - they damp power-supply transients on the die and reduce active power, though they raise leakage power.
• Apply clock gating, XOR self-gating, power gating and multibit flops to address dynamic power.
• Use area-recovery optimization to downsize the drive strength of non-critical paths, which lowers their input pin capacitance and therefore the load capacitance, reducing dynamic power.
• Provide a SAIF file (containing static probability and toggle rate for each signal net; SDC carries this for clock nets) from gate-level or RTL simulation, or annotate set_switching_activity, then enable power_low_power_placement and set_dynamic_optimization so the tool shortens high-switching nets.
• Remove unnecessary pessimism in setup/hold uncertainties and use POCV, which lowers instance count and the associated internal short-circuit power.
• Apply logic restructuring such as Boolean factoring on high-activity nets to reduce the number of logic fanouts on those nets.
• Use pin swapping - in cells where functionally equivalent pins have different input capacitances, move the high-activity net to the lower-capacitance pin.