Floorplanning & Placement

Ground-up guide to CMOS circuit design — transistors, gates, delay, power, memory, datapath and test

Deciding Where Everything Goes

Once the logic is known, it must be given a place on the chip. This is the physical design stage, and it starts with two steps: floorplanning (deciding the big picture) and placement (deciding where each cell sits). Get these right and the chip is fast, small, and routable. Get them wrong and no amount of later effort can save it. This chapter explains both in plain words. It covers blocks and partitions, the power grid, placement goals, congestion, and the link between placement and timing.

Floorplanning — the Big Picture

Floorplanning sets the overall layout. It decides where the large blocks go: memories, processor cores, big functional units. It places the I/O ring around the edge. It reserves channels for power and major wiring. It is the chip's master plan. Good floorplanning groups things that talk to each other. Two blocks that exchange lots of data should sit close, so the wires between them stay short. Memories often go near the logic that uses them. The aim is to shorten the busiest connections before any detailed work begins.

Worked example — distance and delay

Two blocks exchange data over a wire. Placed 3 mm apart, the wire delay is 0.9 ns. Re-placed 1 mm apart:

wire delay scales roughly with length (with repeaters)
0.9 ns × (1 / 3) ≈ 0.3 ns
saving ≈ 0.6 ns just from better placement

Shortening that link by good floorplanning saves more than any cell could. This is why the big picture matters most.

The Power Grid

Before cells are placed, the chip needs a way to feed them power evenly. A power grid is laid down: a mesh of wide metal wires carrying supply and ground across the whole die. Every region taps into this grid. The grid must be strong enough that distant cells still get full voltage. If the grid is too thin, current flowing through it drops voltage along the way (IR drop), and starved cells run slow. So the grid is planned early and checked often.

Worked example — IR drop budget

The grid carries 8 A across a resistance of 5 milliohm from edge to centre.

IR drop = current × resistance = 8 A × 0.005 Ω = 0.040 V = 40 mV

A 40 mV drop on a 0.8 V supply is 5% — usually acceptable. Double the current or halve the grid metal and it climbs to a level that hurts timing. The grid is sized to keep this drop small.

Placement — Putting Cells Down

Placement decides where each standard cell sits within the rows. It is an enormous puzzle: millions of cells, each with many connections, all competing for space. The tool places them to meet several goals at once. The main goals: keep connected cells close (short wires, less delay and power), spread cells so no area is overcrowded, and leave room for the wiring that must follow. These goals conflict — packing cells tight shortens wires but blocks routing — so placement is a careful balance.

Congestion

Congestion is when too many wires want to pass through one area. The cells may fit, but the wires cannot. A congested region cannot be fully routed, and the chip fails. Placement must avoid creating congestion. The tool estimates wiring demand as it places, and spreads cells out of regions that would jam. Sometimes it deliberately leaves a busy block a little loose so its many wires have room to escape. Spotting and fixing congestion early is far cheaper than discovering it during routing.

Worked example — congestion check

A routing region offers 200 wire tracks. The placement there demands 240.

demand / supply = 240 / 200 = 1.20 → 120% utilization
over 100% → not routable; must spread cells out

At 120% demand the region cannot route. The tool must move some cells away until demand drops below the track supply.

Placement and Timing Are Linked

Placement directly sets wire lengths, and wire length sets delay. So placement is really a timing decision in disguise. A critical path whose cells are scattered will have long wires and miss timing. The same path with its cells clustered will be fast. Modern placement is timing-driven: the tool knows which paths are critical and pulls their cells together first. Less critical logic is placed around them. This is why placement and timing closure go hand in hand, looping until both the wiring fits and the speed target is met.

Worked example — timing-driven gain

A critical path has 0.5 ns of slack shortfall. Clustering its cells cuts its total wire length by 40%, and wires were half its delay.

wire delay reduction = 0.40 × (half the path) = 0.20 of the path delay
if path delay was 2.5 ns → save ≈ 0.5 ns
shortfall closed

Good timing-driven placement closes the gap with no logic change at all.

Interview Q&A

cores, functional units) go, where the I/O ring sits, and where power and major wiring channels run. The aim is to place communicating blocks close together so the busiest connections stay short before any detailed work begins.

wide supply and ground wires is laid down first. If the grid is too thin, current flowing through it causes IR drop that starves distant cells and slows them, so it is sized early and rechecked to keep that drop small.

power wires; spread cells so no area is overcrowded; and leave room for the routing that follows. These conflict because packing tight shortens wires but blocks routing, so placement balances them, giving critical paths priority.

through a region than there are tracks for; the cells fit but the wires cannot, so the chip fails to route. Placement estimates wiring demand and spreads cells out of regions that would jam, because fixing it early is far cheaper than during routing.

so placement is effectively a timing decision. A critical path with scattered cells has long wires and misses timing, while clustering those cells makes it fast — which is why placement is timing-driven and loops with timing closure.

cells, it shortens their wires and thus their delay. If wires were a large share of the path delay, that reduction alone can recover the needed slack — e.g. a 40% wire-length cut on a wire-heavy path can save half a nanosecond without touching the logic.

Key Takeaways

• Floorplanning sets the big picture — block positions, I/O ring, power channels — to keep busy links short.
• The power grid is planned early; a weak grid causes IR drop that starves and slows cells.
• Placement balances short wires, even spreading, and routing room, prioritising critical paths.
• Congestion (more wires than tracks) blocks routing; placement spreads cells to prevent it.
• Placement is timing-driven because wire length sets delay — clustering a critical path can close timing with no logic change.