KEY Reduce dynamic power via lower V,f, less switching, shorter nets, clock gating, sizing, SAIF-driven optimization and pin swapping.

Source of the Activity Factor The activity factor is obtained from a VCD or a SAIF file. KEY Activity factor comes from a VCD or SAIF file.

Activity Factor for Input Ports The activity factor for input ports is taken from a VCD file when available; otherwise, based on IO constraints, a default toggle assumption of around 30% per clock cycle is used. KEY Input-port activity comes from a VCD, or defaults to about 30% per clock cycle from IO constraints.

Limitations on Power Vias

• The via array is chosen based on the metal width.
• Via stacking is selected according to what the technology permits. KEY Power-via arrays are picked by metal width and via stacking is limited by technology rules.

Choosing Metal Layers for Power Planning

• The operating frequency.
• The architecture - CPU, DSP and the switching behavior it implies.
• The IR-drop target. KEY Metal-layer choice for power planning depends on frequency, architecture/switching and IR drop.

Spotting the Need for Power Switches The UPF file will contain a create_power_switch command with its control signal specified. KEY A create_power_switch command in the UPF indicates the design needs power switches.