library characterization is done with DRVs in mind. The main DRVs are max_transition, max_capacitance and max_fanout, which capture input slew, output load, drive capability, routing and congestion. They are checked at every stage and must be fixed if they exceed target. KEY DRC = layout obeys foundry rules; DRV = max tran/cap/fanout limits that characterize design quality.

Role of ERC in VLSI ERC stands for Electrical Rule Check. It is run to catch connections considered fatal or dangerous - for example a shorted output, an unconnected input, gates tied directly to the supplies, or potential ESD damage in the design. KEY ERC (Electrical Rule Check) flags dangerous connections like shorted outputs or floating inputs.