KEY Validate the SDC by checking multi-cycle paths, synchronizer constraints and all declared false paths.

AND Gate With No Timing Arc

• Paths going through that AND cell will fail, because the tool cannot see or optimize them.
• The log file issues warnings reporting the missing timing arc.

KEY A missing timing arc makes paths through that cell unoptimized and failing, with warnings logged.

The -combinational Option in create_generated_clock

• By default, create_generated_clock traces the generated clock through sequential cells.
• With the -combinational option specified, the generated clock is instead traced through combinational cells.

KEY create_generated_clock traces through sequential cells by default, -combinational traces through combinational cells.

Why Tap Cells Are Required

• They address the latch-up issue.
• Tap cells came into use around the 65nm node.
• Above 65nm, each standard cell had its own body connection.
• Shrinking standard cells while keeping a body-bias contact in each one became difficult.
• A body-bias connection is needed at regular micron intervals.
• Moving the body-bias contact into a separate cell made the CMOS cells easier to shrink.
• The tap cell supplies that body-bias connection.
• Placing tap cells in a checkerboard pattern roughly halves the total number needed.

KEY Tap cells supply body bias to prevent latch-up and let standard cells shrink, placed in a checkerboard pattern.