across CL.

When Vin = Vdd: if Vg = 0, the Vin terminal acts as the drain and the CL terminal as the source, so Vgs = 0 and the NMOS is off with output 0. As the output rises, Vs = Vdd, so the NMOS is on (Vgs > Vt) and charges CL toward Vdd - but charging stops at Vdd - Vt, because at that point Vgs falls to Vt. So the output is attenuated by Vt and never reaches the full Vdd - a key disadvantage of the NMOS transmission gate.

When Vin = 0: the Vin terminal acts as the source and the CL terminal as the drain. With Vg = Vdd, Vgs = Vdd, so the NMOS is on and CL discharges through the NMOS to the source, giving output 0. So the NMOS passes a good logic 0. Because it cannot pass a good logic 1, the NMOS alone is not used as a transmission gate.

CMOS transmission gate: built from an NMOS and a PMOS in parallel with complementary gate signals. Its advantage over the NMOS-only gate is that the input is transmitted to the output without threshold-voltage attenuation, and the gate delay is almost independent of the input voltage level.

A beta ratio of about 1 is acceptable because when the transmission gate is on, both the PMOS and NMOS conduct in parallel. Even though the PMOS only passes a strong 1 and the NMOS a strong 0, each weakly passes the opposite level, so the combined average resistance is lower than with a single device. Hence a beta of around 1 to 1.5 suffices rather than the beta of 2 used in a CMOS inverter, so PMOS and NMOS can have equal area.

KEY In a CMOS transmission gate both devices conduct in parallel, so a beta near 1 suffices and PMOS/NMOS share equal area.

Tapping N-Well to VDD, Substrate to VSS

Tapping the N-well to VDD and the P-substrate to VSS keeps the drain-to-N-well and source-to-P-substrate junctions reverse-biased, preventing them from becoming forward-biased.