HDL Models of Combinational Circuits
How combinational logic is written in Verilog — and a few classic pitfalls.
Description
Verilog/SystemVerilog descriptions of combinational functions. RTL is how real combinational blocks are specified and synthesized. Use assign for expressions, or always @(*) with every output assigned on every path.
- Dataflow: assign y = a & b; (continuous).
- Behavioral: always @(*) begin … end with full case/if coverage.
- Avoid inferred latches: assign every output on every branch.
- What: Verilog/SystemVerilog descriptions of combinational functions.
- Why: RTL is how real combinational blocks are specified and synthesized.
- How: Use assign for expressions, or always @(*) with every output assigned on every path.
- Where: All combinational RTL in ASIC/FPGA projects.
- When: Whenever combinational behavior is captured for synthesis.
- Analogy — Writing combinational RTL is like filling a form with NO blanks allowed: leave one output unset on some path and the tool 'remembers' the old value — an accidental latch you never wanted.
At a glance
What
Verilog/SystemVerilog descriptions of combinational functions.
Why
RTL is how real combinational blocks are specified and synthesized.
How
Use assign for expressions, or always @(*) with every output assigned on every path.
Where
All combinational RTL in ASIC/FPGA projects.
When
Whenever combinational behavior is captured for synthesis.
Think of it like…
Writing combinational RTL is like filling a form with NO blanks allowed: leave one output unset on some path and the tool 'remembers' the old value — an accidental latch you never wanted.
Two styles
- Dataflow: assign y = a & b; (continuous).
- Behavioral: always @(*) begin … end with full case/if coverage.
- Avoid inferred latches: assign every output on every branch.
Combinational HDL checklist
| Concern | Rule |
|---|---|
| Sensitivity | use @(*) (all inputs) |
| Completeness | assign outputs on every path |
| No latches | include else / default |
| Blocking | use = in combinational blocks |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
The 5 Whys
- 1
Why model in HDL? To simulate and synthesize combinational logic.
- 2
Why @(*)? Missing an input creates simulation/synthesis mismatch.
- 3
Why assign every path? An unassigned output infers an unwanted latch.
- 4
Why blocking '='? It matches combinational dataflow semantics.
- 5
Root cause: combinational intent must be expressed completely or the tool infers memory.
Cheat sheet
Working principle
- Use assign for expressions, or always @(*) with every output assigned on every path.
- Verilog/SystemVerilog descriptions of combinational functions.
Formulas & Boolean expressions
- Dataflow: assign y = a & b; (continuous).
- Sensitivity = use @(*) (all inputs)
- Completeness = assign outputs on every path
- No latches = include else / default
- Blocking = use = in combinational blocks
Key facts
- Dataflow: assign y = a & b; (continuous).
Why it exists
- Root cause: combinational intent must be expressed completely or the tool infers memory.