Mixing VT Types in the Clock Tree

Each VT type has a different sensitivity to design variation, so mixing them in the clock tree makes the tree behave inconsistently under that variation.

KEY Different VT types react differently to variation, so the clock tree must use a single VT type.

Fixing Clock-Gating-Cell Violations

Done automatically by the tool: apply useful skew by adding float-pin constraints on every start point of the violating CGC, with the skew amount set according to the size of the violation.

KEY CGC violations are fixed automatically with useful skew via float-pin constraints sized to the violation.

Checks Done at the CTS Stage

• All cells are legally placed (macros were already checked before placement).
• The tile comes from the technology file.
• The design is divided into a placement grid based on the site or tile.
• Cell families: eg. HD and HP; HP112T cells give performance at the cost of power and area.
• Area-oriented designs use HD17T cells at the cost of performance.
• An area design that still needs high performance may use 12T cells, since performance is the main target.
• Battery-operated devices target 7T/HD cells; for high performance, 7T at the cost of larger area.
• Crossbar (Xbar) architectures are net-dominated and have a maximum utilization below about 50%.
• Designs can be cell-dominated or net-dominated; starting utilization depends on the architecture and the given shape.
• Timing is checked - WNS (worst negative slack), TNS and FEP (failing endpoints).
• Timing and congestion are expected to degrade in later stages, mainly because of routing estimation done at placement.