Derating the Clock Path

It can be done, but it would not be as accurate as derating the data path, so it is generally avoided.

KEY Possible, but less accurate than data-path derating - so it's avoided.

The MMMC File

• The Multi-Mode Multi-Corner (MMMC) file lets the design be analysed across all relevant modes and corners together.
• A design can run in functional, test and other modes, each at different process corners.
• It ensures the design is stable across every PVT corner (process, voltage, temperature).
• The PnR tool reads the MMMC file to pick up all the model/corner detail needed for implementation.

KEY MMMC bundles every mode and corner so the design is verified stable across all PVT conditions.

Timing DRVs - Causes and Fixes

Timing DRVs are max transition, max capacitance and max fanout violations. Causes:

• HVT cells switch slowly, giving large transitions.
• A weak driver cannot drive its load, worsening transition and delay.
• Excess load beyond the cell's characterised max-cap causes bad transition.
• Long nets add resistance, worsening transition and adding to the load (max-cap).
• Excessive fanout exceeds the driver's capability, causing max-fanout and indirectly max-cap/max-tran.

Fixes:

• Max transition - swap HVT for LVT, upsize the driver, split long nets with buffers, reduce load.
• Max cap - upsize the driver, buffer long nets, reduce fanout or