Memory Decoding
How address bits are turned into one active word line, and how chips combine.
Description
Memory decoding converts the address into a single active word line using a decoder, often split into row and column decoders (coincident selection) to keep the decoder small. Larger memories are built by combining chips, using high-order address bits and chip-enable lines to select which chip responds.
- A 2D array uses a row decoder and a column decoder.
- A cell is selected only where its row and column lines coincide.
- Two √N decoders replace one huge N decoder — far fewer gates.
- Row line activates a whole word; column logic routes the bits.
- This is why memory arrays are drawn as squares.
- Stack chips for more words: high-order address bits + a decoder pick the chip via CE.
- Place chips side by side for wider words: share address, concatenate data buses.
- Only the enabled chip drives the (shared) data bus; others go high-impedance.
- Address map = which ranges land on which chip.
- Tri-state outputs let many chips share one bus safely.
At a glance
What
The logic that maps an address to exactly one selected memory cell/word.
Why
A flat decoder for big memory is impractical; structured decoding keeps it small and square.
How
Split address into row + column (coincident selection); use high bits + CE to pick a chip.
Where
Inside every memory array and across multi-chip memory systems.
When
Whenever an address must select a unique location.
Think of it like…
Coincident selection is like seat numbers at a stadium: a row letter and a seat number together pick exactly one seat — far fewer signs than numbering every seat uniquely.
Coincident selection
- A 2D array uses a row decoder and a column decoder.
- A cell is selected only where its row and column lines coincide.
- Two √N decoders replace one huge N decoder — far fewer gates.
- Row line activates a whole word; column logic routes the bits.
- This is why memory arrays are drawn as squares.
Building bigger memory
- Stack chips for more words: high-order address bits + a decoder pick the chip via CE.
- Place chips side by side for wider words: share address, concatenate data buses.
- Only the enabled chip drives the (shared) data bus; others go high-impedance.
- Address map = which ranges land on which chip.
- Tri-state outputs let many chips share one bus safely.
Expanding memory
| Goal | Technique |
|---|---|
| More words | high address bits + CE decoder |
| Wider words | parallel chips, shared address |
| Shared bus | tri-state outputs |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
Decoder picks one line (memory addressing)
▶ live simulatorCode 00 = activates D0 (one-hot).
Real-world applications
The 5 Whys
- 1
Why decode at all? To pick one location from many with few wires.
- 2
Why row+column? Two small decoders beat one giant one.
- 3
Why chip-enable? To select among multiple memory chips.
- 4
Why tri-state? So chips can share one data bus.
- 5
Root cause: structured decoding makes large memories buildable and combinable.
Cheat sheet
Working principle
- Split address into row + column (coincident selection); use high bits + CE to pick a chip.
- The logic that maps an address to exactly one selected memory cell/word.
Formulas & Boolean expressions
- Address map = which ranges land on which chip.
- More words = high address bits + CE decoder
- Wider words = parallel chips, shared address
- Shared bus = tri-state outputs
Key facts
- A 2D array uses a row decoder and a column decoder.
- Stack chips for more words: high-order address bits + a decoder pick the chip via CE.
Why it exists
- Root cause: structured decoding makes large memories buildable and combinable.